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| 10-bit, 105 msps/125 msps/150 msps, 1.8 v dual analog-to-digital converter AD9600 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features snr = 60.6 dbc (61.6 dbfs) to 70 mhz at 150 msps sfdr = 81 dbc to 70 mhz at 150 msps low power: 825 mw at 150 msps 1.8 v analog supply operation 1.8 v to 3.3 v cmos output supply or 1.8 v lvds supply integer 1 to 8 input clock divider intermediate frequency (if) samp ling frequencies up to 450 mhz internal analog-to-digital converter (adc) voltage reference integrated adc sample-and-hold inputs flexible analog input: 1 v p-p to 2 v p-p range differential analog inputs with 650 mhz bandwidth adc clock duty cycle stabilizer 95 db channel isolation/crosstalk serial port control user-configurable built-in self-test (bist) capability energy-saving power-down modes integrated receive features fast detect/threshold bits composite signal monitor applications point-to-point radio receivers (gpsk, qam) diversity radio systems i/q demodulation systems smart antenna systems digital predistortion general-purpose software radios broadband data applications data acquisition nondestructive testing product highlights 1. integrated dual, 10-bit, 150 msps/125 msps/105 msps adc. 2. fast overrange detect and signal monitor with serial output. 3. signal monitor block with dedicated serial output mode. 4. proprietary differential input maintains excellent snr performance for input frequencies up to 450 mhz. 5. the AD9600 operates from a single 1.8 v supply and features a separate digital output driver supply to accommodate 1.8 v to 3.3 v logic families. 6. a standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock dcs, power-down mode, and voltage reference mode. 7. the AD9600 is pin compatible with the ad9627-11 , ad96 27, and ad9640 , allowing a simple migration from 10 bits to 11 bits, 12 bits, or 14 bits. functional block diagram 0 6909-001 signal monitor sha adc cmos/lvds output buffer d9a d0a vin + a vin ? a drvdd dvdd avdd csb sclk/ dfs spi programming data sdio/ dcs fd[0:3]a fd bits/threshold detect sha adc cmos/lvds output buffer d0b d9b vin + b vin ? b dcoa dcob clk+ clk? dco generation duty cycle stablizer divide 1 to 8 drgnd sync agnd smi sdo/ oeb smi sclk/ pdwn serial monitor data smi sdfs serial monitor interface fd[0:3]b fd bits/threshold detect multichip sync vref sense cml ?+ reference select AD9600 notes 1. pin names are for the cmos pin configuration only; see figure 7 for lvds pin names. figure 1.
AD9600 rev. 0 | page 2 of 72 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 ac specifications .......................................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 8 timing characteristics ................................................................ 9 timing diagrams .......................................................................... 9 absolute maximum ratings .......................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 equivalent circuits ......................................................................... 16 typical performance characteristics ........................................... 17 theory of operation ...................................................................... 22 adc architecture ...................................................................... 22 analog input considerations .................................................... 22 volt age reference ....................................................................... 24 clock input considerations ...................................................... 25 power dissipation and standby mode ..................................... 27 digital outputs ........................................................................... 27 timing .......................................................................................... 28 adc overrange and gain control .............................................. 29 fast detect overview ................................................................. 29 adc fast magnitude ................................................................. 29 adc overrange (or) ................................................................ 30 gain switching ............................................................................ 30 signal monitor ................................................................................ 32 peak detector mode ................................................................... 32 rms/ms magnitude mode ....................................................... 32 threshold crossing mode ......................................................... 33 additional control bits ............................................................. 33 dc correction ............................................................................ 34 signal monitor sport output ................................................ 34 built-in self-test (bist) and output test .................................. 35 built-in self-test (bist) ............................................................ 35 output test modes ..................................................................... 35 channel/chip synchronization .................................................... 36 serial port interface (spi) .............................................................. 37 configuration using the spi ..................................................... 37 hardware interface ..................................................................... 37 configuration without the spi ................................................ 38 spi accessible features .............................................................. 38 memory map .................................................................................. 39 reading the memory map table .............................................. 39 memory map .............................................................................. 40 memory map register description ......................................... 43 applications ..................................................................................... 46 design guidelines ...................................................................... 46 evaluation board ............................................................................ 47 power supplies ............................................................................ 47 input signals ................................................................................ 47 output signals ............................................................................ 47 default operation and jumper selection settings ................. 48 alternative clock configurations ............................................ 48 alternative analog input drive configuration ...................... 49 schematics ................................................................................... 50 evaluation board layouts ......................................................... 60 bill of materials ........................................................................... 68 outline dimensions ....................................................................... 70 ordering guide .......................................................................... 70 revision history 11/07revision 0: initial version AD9600 rev. 0 | page 3 of 72 general description the AD9600 is a dual, 10-bit, 105 msps/125 msps/150 msps adc. it is designed to support communications applications where low cost, small size, and versatility are desired. the dual adc core features a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer is provided to compen- sate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. the AD9600 has several functions that simplify the automated gain control (agc) function in a communications receiver. for example, the fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. in addition, the programmable threshold detector allows moni- toring the amplitude of the incoming signal with short latency, using the four fast detect bits of the adc. if the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. because this threshold is set from the four msbs, the user can quickly adjust the system gain to avoid an overrange condition. another agc-related function of the AD9600 is the signal monitor. this block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. the adc output data can be routed directly to the two external 10-bit output ports. these outputs can be set from 1.8 v to 3.3 v cmos or 1.8 v lvds. in addition, flexible power-down options allow significant power savings. AD9600 rev. 0 | page 4 of 72 specifications dc specifications avdd = 1.8 v, dvdd = 1.8 v, drvdd = 3.3 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, d cs enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted. table 1. AD9600bcpz-105 AD9600bcpz-125 AD9600bcpz-150 parameter temp min typ max min typ max min typ max unit resolution full 10 10 10 bits accuracy no missing codes full guarant eed guaranteed guaranteed offset error full 0.3 0.7 0.3 0.7 0.3 0.7 % fsr gain error full ?3.6 ?2.2 ?1.0 ?4.0 ?2.5 ?1.3 ?4.3 ?3.0 ?1.6 % fsr differential nonlinearity (dnl) 1 full 0.2 0.2 0.2 lsb 25c 0.1 0.1 0.1 lsb integral nonlinearity (inl) 1 full 0.3 0.3 0.4 lsb 25c 0.1 0.1 0.1 lsb matching characteristics offset error full 0.3 0.7 0.3 0.7 0.2 0.7 % fsr gain error full 0.2 0.8 0.3 0.8 0.2 0.8 % fsr temperature drift offset error full 15 15 15 ppm/c gain error full 95 95 95 ppm/c internal voltage reference output voltage error (1 v mode) full 5 16 5 16 5 16 mv load regulation @ 1.0 ma full 7 7 7 mv input-referred noise vref = 1.0 v 25c 0.1 0.1 0.1 lsb rms analog input input span, vref = 1.0 v full 2 2 2 v p-p input capacitance 2 full 8 8 8 pf vref input resistance full 6 6 6 k power supplies supply voltage avdd, dvdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd (cmos mode) full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 v supply current i avdd 1 , 3 full 310 365 385 455 419 495 ma i dvdd 1 , 3 , 4 full 34 365 42 455 50 495 ma i drvdd (3.3 v cmos) full 35 36 42 ma i drvdd (1.8 v cmos) full 15 18 22 ma i drvdd (1.8 v lvds) 42 44 46 ma power consumption dc input full 600 650 750 800 825 890 mw sine wave input 1 drvdd = 1.8 v full 645 813 892 mw drvdd = 3.3 v full 740 900 990 mw standby power 4 full 68 77 77 mw power-down power full 2.5 6 2.5 6 2.5 6 mw 1 measured with a low input frequency, full-scale sine wa ve, with approximately 5 pf load ing on each output bit. 2 input capacitance refers to the effectiv e capacitance between one differential input pin and agnd. refer to figure 8 for the e quivalent analog input structure. 3 the maximum limit applies to the combination of i avdd and i dvdd currents. 4 standby power is measured with a dc input and the clk+ and clk? pins inactive (set to avdd or agnd). AD9600 rev. 0 | page 5 of 72 ac specifications avdd = 1.8 v, dvdd = 1.8 v, drvdd = 3.3 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, d cs enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted. table 2. AD9600bcpz-105 AD9600bcpz-125 AD9600bcpz-150 parameter 1 temp min typ max min typ max min typ max unit signal-to-noise ratio (snr) f in = 2.3 mhz 25c 60.7 60.6 60.6 db f in = 70 mhz 25c 60.6 60.6 60.6 db full 60.3 60.3 60.3 db f in = 140 mhz 25c 60.6 60.6 60.5 db f in = 220 mhz 25c 60.5 60.5 60.4 db signal-to-noise and distortion (sinad) f in = 2.3 mhz 25c 60.6 60.5 60.5 db f in = 70 mhz 25c 60.5 60.5 60.5 db full 60.2 60.2 60.1 db f in = 140 mhz 25c 60.5 60.5 60.4 db f in = 220 mhz 25c 60.4 60.4 60.3 db effective number of bits (enob) f in = 2.3 mhz 25c 9.9 9.9 9.9 bits f in = 70 mhz 25c 9.9 9.9 9.9 bits f in = 140 mhz 25c 9.9 9.9 9.9 bits f in = 220 mhz 25c 9.9 9.9 9.9 bits worst second or third harmonic f in = 2.3 mhz 25c ?87.0 ?86.5 ?88.5 dbc f in = 70 mhz 25c ?85.0 ?85.0 ?84.0 dbc full ?72.0 ?72.0 ?72.0 dbc f in = 140 mhz 25c ?84.0 ?84.0 ?83.5 dbc f in = 220 mhz 25c ?83.0 ?83.0 ?77 dbc spurious-free dynamic range (sfdr) f in = 2.3 mhz 25c 85.5 85.5 85.5 dbc f in = 70 mhz 25c 85.0 85.0 84.0 dbc full 72.0 72.0 72.0 dbc f in = 140 mhz 25c 83.0 84.0 83.5 dbc f in = 220 mhz 25c 81.0 81.0 77 dbc worst other harmonic or spur f in = 2.3 mhz 25c ?92 ?92 ?92 dbc f in = 70 mhz 25c ?88 -88 ?88 dbc full ?81 ?81 ?80 dbc f in = 140 mhz 25c ?86 ?86 ?86 dbc f in = 220 mhz 25c ?86 ?86 ?86 dbc two-tone sfdr f in = 29.1 mhz, 32.1 mhz (?7 dbfs ) 25c 84 84 84 dbc f in = 169.1 mhz, 172.1 mhz (?7 dbfs ) 25c 82 82 82 dbc crosstalk 2 full 95 95 95 db analog input bandwidth 25c 650 650 650 mhz 1 see an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1 dbfs on one channel an d no input on the alternate channel. AD9600 rev. 0 | page 6 of 72 digital specifications avdd = 1.8 v, dvdd = 1.8 v, drvdd = 3.3 v, maximum sample rate, ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless otherwise noted. table 3. parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 1.2 v differential input voltage full 0.2 6 v p-p input voltage range full gnd ? 0.3 avdd + 1.6 v input common-mode range full 1.1 avdd v high level input voltage full 1.2 3.6 v low level input voltage full 0 0.8 v high level input current full ?10 +10 a low level input current full ?10 +10 a input capacitance full 4 pf input resistance full 8 10 12 k sync input logic compliance cmos internal bias full 1.2 v input voltage range full gnd ? 0.3 avdd + 1.6 v high level input voltage full 1.2 3.6 v low level input voltage full 0 0.8 v high level input current full ?10 +10 a low level input current full ?10 +10 a input capacitance full 4 pf input resistance full 8 10 12 k logic input (csb) 1 high level input voltage full 1.22 3.6 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 40 132 a input resistance full 26 k input capacitance full 2 pf logic input (sclk/dfs) 2 high level input voltage full 1.22 3.6 v low level input voltage full 0 0.6 v high level input current (vin = 3.3 v) full ?92 ?135 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 2 pf logic inputs/outputs (sdio/dcs, smi sdfs) 1 high level input voltage full 1.22 3.6 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 38 128 a input resistance full 26 k input capacitance full 5 pf AD9600 rev. 0 | page 7 of 72 parameter temperature min typ max unit logic inputs/outputs (smi sdo/oeb, smi sclk/pdwn) 2 high level input voltage full 1.22 3.6 v low level input voltage full 0 0.6 v high level input current (vin = 3.3 v) full ?90 ?134 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 5 pf digital outputs cmos modedrvdd = 3.3 v high level output voltage (i oh = 50 a) full 3.29 v high level output voltage (i oh = 0.5 ma) full 3.25 v low level output voltage (i ol = 1.6 ma) full 0.2 v low level output voltage (i ol = 50 a) full 0.05 v cmos modedrvdd = 1.8 v high level output voltage (i oh = 50 a) full 1.79 v high level output voltage (i oh = 0.5 ma) full 1.75 v low level output voltage (i ol = 1.6 ma) full 0.2 v low level output voltage (i ol = 50 a) full 0.05 v lvds modedrvdd = 1.8 v differential output voltage (v od ), ansi mode full 250 350 450 mv output offset voltage (v os ), ansi mode full 1.15 1.25 1.35 v differential output voltage (v od ), reduced swing mode full 150 200 280 mv output offset voltage (v os ), reduced swing mode full 1.15 1.25 1.35 v 1 pull up. 2 pull down. AD9600 rev. 0 | page 8 of 72 switching specifications avdd = 1.8 v, dvdd = 1.8 v, drvdd = 3.3 v, maximum sample rate, ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless otherwise noted. table 4. AD9600bcpz-105 AD9600bcpz-125 AD9600bcpz-150 parameter temp min typ max min typ max min typ max unit clock input parameters input clock rate full 625 625 625 mhz conversion rate dcs enabled full 20 105 20 125 20 150 msps dcs disabled full 10 105 10 125 10 150 msps clk period (t clk ) full 9.5 8 6.66 ns clk pulse width high divide-by-1 mode, dcs enabled full 2.85 4.75 6.65 2.4 4 5.6 2.0 3.33 4.66 ns divide-by-1 mode, dcs disabled full 4.28 4.75 5.23 3.6 4 4.4 3.0 3.33 3.66 ns divide-by-2 mode, dcs enabled full 1.6 1.6 1.6 ns divide-by-3 through divide- by-8 modes, dcs enabled full 0.8 0.8 0.8 ns data output parameters cmos modedrvdd = 3.3 v data propagation delay (t pd ) 1 full 2.2 4.5 6.4 2.2 4. 5 6.4 2.2 4.5 6.4 ns dco propagation delay (t dco ) full 3.8 5.0 6.8 3.8 5. 0 6.8 3.8 5.0 6.8 ns setup time (t s ) full 5.25 4.5 3.83 ns hold time (t h ) full 4.25 3.5 2.83 ns cmos modedrvdd = 1.8 v data propagation delay (t pd ) 1 full 2.4 5.2 6.9 2.4 5. 2 6.9 2.4 5.2 6.9 ns dco propagation delay (t dco ) full 4.0 5.6 7.3 4.0 5. 6 7.3 4.0 5.6 7.3 ns setup time (t s ) full 5.25 4.5 3.83 ns hold time (t h ) full 4.25 3.5 2.83 ns lvds modedrvdd = 1.8 v full data propagation delay (t pd ) 1 2.0 4.8 6.3 2.0 4.8 6.3 2.0 4.8 6.3 ns dco propagation delay (t dco ) full 5.2 7.3 9.0 5.2 7. 3 9.0 5.2 7.3 9.0 ns cmos mode pipeline delay (latency) full 12 12 12 cycles lvds mode pipeline delay (latency) channel a/channel b full 12/12.5 12/12.5 12/12.5 cycles aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 0.1 ps rms wake-up time 2 full 350 350 350 s out-of-range recovery time full 2 3 3 cycles 1 output propagation delay is measured from the clk+ and clk? pins 50% transition to the output data pins 50% transition, with 5 pf load. 2 wake-up time is dependent on the value of the decoupling capacitors. AD9600 rev. 0 | page 9 of 72 timing characteristics table 5. parameter conditions min typ max unit sync timing requirements t ssync setup time between sync and the rising edge of clk+ 0.24 ns t hsync hold time between sync and the rising edge of clk+ 0.40 ns spi timing requirements t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high sclk pulse width high 10 ns t low sclk pulse width low 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns sport timing requirements t cssclk delay from the rising edge of clk+ to the rising edge of smi sclk 3.2 4.5 6.2 ns t ssclksdo delay from the rising edge of smi sclk to smi sdo ?0.4 0 0.4 ns t ssclksdfs delay from the rising edge of smi sclk to smi sdfs ?0.4 0 0.4 ns timing diagrams 06909-012 clk+ dcoa/dcob ch a/ch b dat a n n+ 1 n+2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7 n+ 8 n ? 12 n ? 11 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 13 clk? t clk t pd t s t h t dco t clk t a ch a/ch b fast detect n ? 1 n + 2 n + 3 n + 4 n + 5 n + 6 n ? 3 n ? 2 n ? 10 n + 1 n figure 2. cmos output mode data and fast detect output timing AD9600 rev. 0 | page 10 of 72 06909-089 clk+ dco+ dco? ch a/ch b data n n+ 1 n+2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7 n+ 8 n ? 12 n ? 11 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 13 clk? t clk t pd t dco t clk t a ch a/ch b fast detect ababababababababa a b n ? 10 n ? 6 n ? 5 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n ? 7 ababababababababa a b n ? 4 figure 3. lvds mode data and fast detect output timing (fast detect mode select bits = 000) sync clk+ t hsync t ssync 06909-072 figure 4. sync input timing requirements clk+ s mi sclk/pdwn smi sdfs data data smi sdo/oeb clk? t cssclk t ssclksdfs t ssclksdo 06909-082 figure 5. signal monitor sport ou tput timing (divide-by-2 mode) AD9600 rev. 0 | page 11 of 72 absolute maximum ratings table 6. parameter rating electrical avdd, dvdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +3.9 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?3.9 v to +2.0 v vin + a/vin + b, vin ? a/vin ? b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to +3.9 v sync to agnd ?0.3 v to +3.9 v vref to agnd ?0.3 v to avdd + 0.2 v sense to agnd ?0.3 v to avdd + 0.2 v cml to agnd ?0.3 v to avdd + 0.2 v rbias to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to +3.9 v sclk/dfs to drgnd ?0.3 v to +3.9 v sdio/dcs to drgnd ?0.3 v to drvdd + 0.3 v smi sdo/oeb ?0.3 v to drvdd + 0.3 v smi sclk/pdwn ?0.3 v to drvdd + 0.3 v smi sdfs ?0.3 v to drvdd + 0.3 v output data pins to drgnd 1 ?0.3 v to drvdd + 0.3 v fast detect output pins to drgnd 2 ?0.3 v to drvdd + 0.3 v data clock output pins to drgnd 3 ?0.3 v to drvdd + 0.3 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +150c 1 the output data pins are d0a/d0b to d9a/d9b for the cmos configuration and d0+/d0? to d9+/d9? for the lvds configuration. 2 the fast detect output pins are fd0a/fd0b to fd3a/fd3b for the cmos configuration and fd0+/fd0? to fd3+/fd3?. 3 the data clock output pins are dcoa and dcob for the cmos configuration and dco+ and dco? for the lvds configuration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7. thermal resistance package type airflow velocity (m/s) ja 1, 2 jc 1, 3 jb 1, 4 unit 0 18.8 0.6 6.0 c/w 64 lead, 9 mm 9 mm lfcsp (cp-64-3) 1.0 16.5 c/w 2.0 15.8 c/w 1 per jedec 51-7 standard and jedec 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal (such as metal traces through holes, ground, and power planes) that is in direct contact with the package leads reduces the ja . esd caution AD9600 rev. 0 | page 12 of 72 pin configuration and fu nction descriptions 06909-002 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d1a d2a d3a drgnd drvdd d4a d5a dvdd d6a d7a d8a (msb) d9a fd0a fd1a fd2a fd3a 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 drgnd d1b d0b (lsb) dnc dnc dnc dnc dvdd fd3b fd2b fd1b fd0b sync csb clk? clk+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 drvdd d2b d3b d4b d5b d6b d7b d8b (msb) d9b dcob dcoa dnc dnc dnc dnc (lsb) d0a sclk/dfs sdio/dcs avdd avdd vin + b vin ? b rbias cml sense vref vin ? a vin + a avdd smi sdfs smi sclk/pdwn smi sdo/oeb 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dnc = do not connect pin 1 indicator AD9600 parallel cmos top view (not to scale) exposed paddle, pin 0 (bottom of package) figure 6. parallel cmos mode pin configuration (top view) table 8. parallel cmos mode pin function descriptions pin no. mnemonic type description adc power supplies 20, 64 drgnd ground digital output ground. 1, 21 drvdd supply digital output driver supply (1.8 v to 3.3 v). 24, 57 dvdd supply digital power supply (1.8 v nominal). 36, 45, 46 avdd supply analog power supply (1.8 v nominal). 0 agnd ground analog ground. pin 0 is the exposed thermal pad on the bottom of the package. adc inputs 37 vin + a input differential analog input pin (+) for channel a. 38 vin ? a input differential analog input pin (?) for channel a. 44 vin + b input differential analog input pin (+) for channel b. 43 vin ? b input differential analog input pin (?) for channel b. 39 vref i/o voltage reference input/output. 40 sense input voltage reference mode select (see table 11 for details). 42 rbias input external reference bias resistor. 41 cml output common-mode level bi as output for analog inputs. 49 clk+ input adc master clock true. the adc clock can be driven using a single-ended cmos (see figure 60 and figure 61 for the recommended connection). 50 clk? input adc master clock complement. the adc clock can be driven using a single- ended cmos (see figure 60 and figure 61 for the recommended connection). adc fast detect outputs 29 fd0a output channel a fast detect indicator (see table 14 for details). 30 fd1a output channel a fast detect indicator (see table 14 for details). 31 fd2a output channel a fast detect indicator (see table 14 for details). 32 fd3a output channel a fast detect indicator (see table 14 for details). 53 fd0b output channel b fast detect indicator (see table 14 for details). 54 fd1b output channel b fast detect indicator (see table 14 for details). 55 fd2b output channel b fast detect indicator (see table 14 for details). 56 fd3b output channel b fast detect indicator (see table 14 for details). AD9600 rev. 0 | page 13 of 72 pin no. mnemonic type description digital inputs 52 sync input digital synchronization pin (slave mode only). digital outputs 16 to 19, 22, 23, 25 to 28 d0a to d9a output channel a cmos output data. 62, 63, 2 to 9 d0b to d9b output channel b cmos output data. 11 dcoa output channel a data clock output. 10 dcob output channel b data clock output. spi control 48 sclk/dfs input spi serial clock/data fo rmat select pin in external pin mode. 47 sdio/dcs i/o spi serial data input and output /duty cycle stabilizer in external pin mode. 51 csb input spi chip select (active low). signal monitor port 33 smi sdo/oeb i/o signal monitor serial data output/o utput enable input (active low) in external pin mode. 35 smi sdfs output signal monitor serial data frame sync. 34 smi sclk/pdwn i/o signal monitor serial clock output/po wer-down input in external pin mode. do not connect 12 to 15, 58 to 61 dnc n/a do not connect. AD9600 rev. 0 | page 14 of 72 06909-003 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d3+ d4? d4+ drgnd drvdd d5? d5+ dvdd d6? d6+ d7? d7+ d8? d8+ d9? (msb) d9+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 drgnd dnc dnc fd3+ fd3? fd2+ fd2? dvdd fd1+ fd1? fd0+ fd0? sync csb clk? clk+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 drvdd dnc dnc dnc dnc dnc dnc (lsb) d0? d0+ dco? dco+ d1? d1+ d2? d2+ d3? dnc = do not connect sclk/dfs sdio/dcs avdd avdd vin + b vin ? b rbias cml sense vref vin ? a vin + a avdd smi sdfs smi sclk/pdwn smi sdo/oeb 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pin 1 indicator AD9600 parallel lvds top view (not to scale) exposed paddle, pin 0 (bottom of package) figure 7. interleaved parallel lvds mode pin configuration (top view) table 9. interleaved parallel lvds mode pin function descriptions pin no. mnemonic type description adc power supplies 20, 64 drgnd ground digital output ground. 1, 21 drvdd supply digital output driver supply (1.8 v to 3.3 v). 24, 57 dvdd supply digital power supply (1.8 v nominal). 36, 45, 46 avdd supply analog power supply (1.8 v nominal). 0 agnd ground analog ground. pin 0 is the expo sed thermal pad on the bottom of the package. adc inputs 37 vin + a input differential analog input pin (+) for channel a. 38 vin ? a input differential analog input pin (?) for channel a. 44 vin + b input differential analog input pin (+) for channel b. 43 vin ? b input differential analog input pin (?) for channel b. 39 vref i/o voltage reference input/output. 40 sense input voltage reference mode select (see table 11 for details). 42 rbias input external reference bias resistor. 41 cml output common-mode level bi as output for analog inputs. 49 clk+ input adc master clock true. the adc clock can be driven using a single-ended cmos (see figure 60 and figure 61 for the recommended connection). 50 clk? input adc master clock complement. the adc clock can be driven using a single-ended cmos (see figure 60 and figure 61 for the recommended connection). adc fast detect outputs 54 fd0+ output channel a/channel b lvds fast detect indicator 0 true (see table 14 for full details). 53 fd0? output channel a/channel b lvds fast detect indicator 0 complement (see table 14 for details). 56 fd1+ output channel a/channel b lvds fast detect indicator 1 true (see table 14 for details). 55 fd1? output channel a/channel b lvds fast detect indicator 1 complement (see table 14 for details). 59 fd2+ output channel a/channel b lvds fast detect indicator 2 true (see table 14 for details). 58 fd2? output channel a/channel b lvds fast detect indicator 2 complement (see table 14 for details). 61 fd3+ output channel a/channel b lvds fast detect indicator 3 true (see table 14 for details). 60 fd3? output channel a/channel b lvds fast detect indicator 3 complement (see table 14 for details). AD9600 rev. 0 | page 15 of 72 pin no. mnemonic type description digital inputs 52 sync input digital synchronization pin (slave mode only). digital outputs 9 d0+ output channel a/channel b lvds output data 0 true. 8 d0? output channel a/channel b lvds output data 0 complement. 13 d1+ output channel a/channel b lvds output data 1 true. 12 d1? output channel a/channel b lvds output data 1 complement. 15 d2+ output channel a/channel b lvds output data 2 true. 14 d2? output channel a/channel b lvds output data 2 complement. 17 d3+ output channel a/channel b lvds output data 3 true. 16 d3? output channel a/channel b lvds output data 3 complement. 19 d4+ output channel a/channel b lvds output data 4 true. 18 d4? output channel a/channel b lvds output data 4 complement. 23 d5+ output channel a/channel b lvds output data 5 true. 22 d5? output channel a/channel b lvds output data 5 complement. 26 d6+ output channel a/channel b lvds output data 6 true. 25 d6? output channel a/channel b lvds output data 6 complement. 28 d7+ output channel a/channel b lvds output data 7 true. 27 d7? output channel a/channel b lvds output data 7 complement. 30 d8+ output channel a/channel b lvds output data 8 true. 29 d8? output channel a/channel b lvds output data 8 complement. 32 d9+ output channel a/channel b lvds output data 9 true. 31 d9? output channel a/channel b lvds output data 9 complement. 11 dco+ output channel a/channel b lvds data clock output true. 10 dco? output channel a/channel b lv ds data clock output complement. spi control 48 sclk/dfs input spi serial clock/data fo rmat select pin in external pin mode. 47 sdio/dcs i/o spi serial data input and output /duty cycle stabilizer in external pin mode. 51 csb input spi chip select (active low). signal monitor port 33 smi sdo/oeb i/o signal monitor serial data output/o utput enable input (active low) in external pin mode. 35 smi sdfs output signal monitor serial data frame sync. 34 smi sclk/pdwn i/o signal monitor serial clock output/po wer-down input in external pin mode. do not connect 2 to 7, 62, 63 dnc n/a do not connect. AD9600 rev. 0 | page 16 of 72 equivalent circuits v in 06909-004 figure 8. analog input circuit 1.2v 10k ? 10k ? c lk+ clk? avdd 0 6909-005 figure 9. equivalent clock input circuit drvdd drgnd 0 6909-081 figure 10. digital output 06909-007 sdio/dcs 1k? 26k ? drvdd drvdd figure 11. equivalent sdio/dcs input circuit 06909-008 sclk/dfs 1k ? 26k ? figure 12. equivalent sclk/dfs input circuit sense 1k? 06909-009 figure 13. equivalent sense circuit csb 1k ? 26k ? a vdd 06909-010 figure 14. equivalent csb input circuit v ref avdd 6k ? 06909-011 figure 15. equivalent vref circuit AD9600 rev. 0 | page 17 of 72 typical performance characteristics avdd = 1.8 v, dvdd = 1.8 v, drvdd = 3.3 v, sample rate = 150 msps, dcs enabled, 1 v internal reference, 2 v p-p differential in put, vin = ?1.0 dbfs, 64k sample, and t a = 25c, unless otherwise noted. amplitude (dbfs) frequency (mhz) 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 second harmonic third harmonic 150msps 2.3mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.9 bits sfdr = 85.5dbc 06909-029 figure 16. AD9600-150 single-tone fft with f in = 2.3 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 30.3mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.9 bits sfdr = 84.0dbc second harmonic 06909-030 figure 17. AD9600-150 single-tone fft with f in = 30.3 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 70mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.8 bits sfdr = 84.0dbc second harmonic 06909-118 figure 18. AD9600-150 single-tone fft with f in = 70 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 140mhz @ ?1dbfs snr = 60.5db (61.5dbfs) enob = 9.8 bits sfdr = 83.5dbc second harmonic 06909-119 figure 19. AD9600-150 single-tone fft with f in = 140 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 220mhz @ ?1dbfs snr = 60.4db (61.4dbfs) enob = 9.7 bits sfdr = 77.0dbc second harmonic 06909-120 figure 20. AD9600-150 single-tone fft with f in = 220 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 337mhz @ ?1dbfs snr = 60.2db (61.2dbfs) enob = 9.7 bits sfdr = 74.0dbc second harmonic 06909-121 figure 21. AD9600-150 single-tone fft with f in = 337 mhz AD9600 rev. 0 | page 18 of 72 amplitude (dbfs) frequency (mhz) third harmonic 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 440mhz @ ?1dbfs snr = 60.0db (61.0dbfs) enob = 9.6 bits sfdr = 70.0dbc second harmonic 06909-122 figure 22. AD9600-150 single-tone fft with f in = 440 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 102030405060 ?120 ?100 ?80 ?60 ?40 ?20 0 125msps 2.3mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.8 bits sfdr = 86.5dbc second harmonic 06909-123 figure 23. AD9600-125 single-tone fft with f in = 2.3 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 102030405060 ?120 ?100 ?80 ?60 ?40 ?20 0 125msps 30.3mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.8 bits sfdr = 85.0dbc second harmonic 06909-124 figure 24. AD9600-125 single-tone fft with f in = 30.3 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 102030405060 ?120 ?100 ?80 ?60 ?40 ?20 0 125msps 70.1mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.8 bits sfdr = 85.0dbc second harmonic 06909-125 figure 25. AD9600-125 single-tone fft with f in = 70.1 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 102030405060 ?120 ?100 ?80 ?60 ?40 ?20 0 125msps 140.1mhz @ ?1dbfs snr = 60.6db (61.6dbfs) enob = 9.8 bits sfdr = 84.0dbc second harmonic 06909-126 figure 26. AD9600-125 single-tone fft with f in = 140.1 mhz amplitude (dbfs) frequency (mhz) third harmonic 0 102030405060 ?120 ?100 ?80 ?60 ?40 ?20 0 125msps 220.1mhz @ ?1dbfs snr = 60.5db (61.5dbfs) enob = 9.7 bits sfdr = 81.0dbc second harmonic 06909-127 figure 27. AD9600-125 single-tone fft with f in = 220.1 mhz AD9600 rev. 0 | page 19 of 72 snr/sfdr (dbc and dbm) amplitude (dbm) ?60 ?10 ?20 ?30 ?40 ?50 0 0 120 100 80 60 40 20 sfdr (dbfs) snr (dbfs) 85db reference line snr (dbc) sfdr (dbc) 06909-031 figure 28. AD9600-150 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 2.4 mhz snr/sfdr (dbc and dbm) amplitude (dbm) ?60 ?10 ?20 ?30 ?40 ?50 0 0 100 80 60 40 20 sfdr (dbfs) snr (dbfs) 85db reference line snr (dbc) sfdr (dbc) 06909-032 figure 29. AD9600-150 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 98.12 mhz snr/sfdr (dbc) input frequency (mhz) 0 50 100 150 200 250 300 350 400 450 55 60 65 70 75 80 85 90 95 snr +25c snr +85c snr ?40c sfdr +25c sfdr ?40c sfdr +85c 06909-033 figure 30. AD9600-150 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 2 v p-p full scale snr/sfdr (dbc) input frequency (mhz) 0 50 100 150 200 250 300 350 400 450 55 60 65 70 75 80 85 90 95 snr +25c snr +85c snr ?40c sfdr ?40c sfdr +85c sfdr +25c 06909-034 figure 31. AD9600-150 single-tone snr/sfdr vs. input frequency (f in ) and temperature with12 v p-p full scale 06909-132 ? 2.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 0.5 0 0.1 0.2 0.3 0.4 ?40 80 60 40 gain offset 20 0 ?20 gain error (%fsr) offset error (%fsr) temperature (c) figure 32. AD9600-150 gain and offset vs. temperature sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?60 ?12 ?24 ?36 ?48 ?120 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 06909-133 figure 33. AD9600-150 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 29.1 mhz, f in2 = 32.1 mhz, f s = 150 msps AD9600 rev. 0 | page 20 of 72 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?60 ?12 ?24 ?36 ?48 ?120 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbc) imd3 (dbc) 06909-134 sfdr (dbfs) imd3 (dbfs) figure 34. AD9600-150 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 169.1 mhz, f in2 = 172.1 mhz, f s = 150 msps 06909-135 0 ?20 ?40 ?60 ?80 ?100 ?120 0 15.36 30.72 46.08 61.44 amplitude (dbfs) frequency (mhz) figure 35. AD9600-125 two 64k wcdma carriers with f in = 170 mhz, f s = 125 msps amplitude (dbfs) input frequency (mhz) 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 29.1mhz @ ?7dbfs 32.1mhz @ ?7dbfs sfdr = 86.1dbc (93.1dbfs) 06909-136 figure 36. AD9600-150 two-tone sfdr/imd3 vs. input frequency (f in ) with f in1 = 29.1 mhz, f in2 = 32.1 mhz, f s = 150 msps amplitude (dbfs) input frequency (mhz) 0 10203040506070 ?120 ?100 ?80 ?60 ?40 ?20 0 150msps 169.1mhz @ ?7dbfs 172.1mhz @ ?7dbfs sfdr = 83.1dbc (90.1dbfs) 06909-137 figure 37. AD9600-150 two-tone sfdr/imd3 vs. input frequency (f in ) with f in1 = 169.1 mhz, f in2 = 172.1 mhz, f s = 150 msps 06909-138 0 ?20 ?40 ?60 ?80 ?100 ?120 07 60 50 40 30 20 10 amplitude (dbfs) frequency (mhz) 0 npr = 54.3dbc notch @ 18.5mhz notch width = 3mhz figure 38. AD9600-150 noise power ratio (npr) snr/sfdr (dbc) encode (msps) 0 25 50 75 100 125 150 50 60 70 80 90 100 sfdr?side b sfdr?side a snr?side a snr?side b 06909-035 figure 39. AD9600-150 single-tone snr/sfdr vs. clock frequency (f s ) with f in1 = 2.3 mhz AD9600 rev. 0 | page 21 of 72 12 10 8 6 4 2 0 n + 3 n + 2 n + 1 n n ? 1 n ? 2 n ? 3 number of hits (1m) output code 0.10 lsb rms 06909-140 figure 40. AD9600 grounded input histogram 06909-143 100 60 65 70 75 80 85 90 95 20 80 60 40 snr/sfdr (dbc) duty cycle (%) sfdr dcs on snr dcs on sfdr dcs off snr dcs off figure 43. AD9600-150 snr/sfdr vs. duty cycle with f in1 = 10.3 mhz 06909-144 95 55 60 65 70 75 80 85 90 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbc) input common-mode voltage (v) snr sfdr inl error (lsb) output code ?0.10 ?0.05 0 0.05 0.10 0 128 256 384 512 640 768 896 1024 06909-036 figure 41. AD9600 inl with f in1 = 10.3 mhz figure 44. AD9600-150 snr/sfdr vs . input common-mode voltage (v cm ) with f in1 = 30 mhz dnl error (lsb) output code ?0.100 ?0.025 ?0.075 ?0.050 0 0.050 0.025 0.075 0.100 0 128 256 384 512 640 768 896 1024 06909-037 figure 42. AD9600 dnl with f in1 = 10.3 mhz AD9600 rev. 0 | page 22 of 72 theory of operation the AD9600 dual adc design can be used for diversity reception of signals, where the adcs are operating identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample any f s /2 frequency segment from dc to 200 mhz using appropriate low-pass or band-pass filtering at the adc inputs with little loss in adc performance. although operation of up to 450 mhz analog input is permitted, adc distortion increases at frequencies toward the higher end of this range. in nondiversity applications, the AD9600 can be used as a baseband receiver where one adc is used for i input data and the other used for q input data. synchronization capability is provided to allow synchronized timing among multiple channels or multiple devices. programming and control of the AD9600 is accomplished using a 3-bit spi-compatible serial interface. adc architecture the AD9600 architecture consists of a dual front-end sample- and-hold amplifier (sha) followed by a pipelined switched- capacitor adc. the quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline excluding the last consists of a low resolution flash adc connected to a switched-capacitor digital- to-analog converter (dac) and an interstage residue amplifier (a multiplying digital-to-analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sha that can be ac- or dc-coupled in differential or single-ended modes. the output-staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. analog input considerations the analog input to the AD9600 is a differential switched- capacitor sha that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches the sha between sample mode and hold mode (see figure 45 ). when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adcs input; therefore, the precise values are dependent on the application. in undersampling (if sampling) applications, any shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. see the an-742 application note , frequency domain response of switched-capacitor adcs ; the an-827 application note , a resonant approach to interfacing amplifiers to switched-capacitor adcs ; and the analog dialogue article transformer-coupled front-end for wideband a/d converters (volume 39, april 2005) for more information. in general, the precise values are dependent on the application. vin+ vin? c pin, par c pin, par c s c s c h c h h s s s s 06909-013 figure 45. switched-c apacitor sha input for best dynamic performance, the source impedances driving vin+ and vin? should be matched. an internal differential reference buffer creates positive and neg- ative reference voltages that define the input span of the adc core. the span of the adc core is set by the buffer to 2 vref . input common mode the analog inputs of the AD9600 are not internally dc-biased. therefore, in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = 0.55 avdd is recommended for optimum performance, but the device can function over a wider range with reasonable performance (see figure 44 ). an on-board common-mode voltage reference is included in the design and is available from the cml pin. optimum performance is achieved when the common-mode voltage of the analog input is set by the cml pin voltage (typically 0.55 avdd). the cml pin must be decoupled to ground by a 0.1 f capacitor as described in the applications section. differential input configurations optimum performance is achieved while driving the AD9600 in a differential input configuration. for baseband applications, the ad8138 , ada4937-2 , and ada4938-2 differential drivers provide excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is AD9600 rev. 0 | page 23 of 72 easily set with the cml pin of the AD9600 (see figure 46 ), and the driver can be configured in a sallen-key filter topology to band limit the input signal. avdd 1v p-p 49.9 ? 523 ? 0.1f r r c 499 ? 499 ? 499 ? ad8138 AD9600 vin+ vin? cml 06909-014 figure 46. differential input configuration using the ad8138 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 47 . the cml voltage can be connected to the center tap of the transformers secondary winding to bias the analog input. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz. excessive signal power can cause core saturation, which leads to distortion. 2 v p-p 49.9 ? 0.1f r r c AD9600 vin+ vin? cml 06909-015 figure 47. differential transformer-coupled configuration at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the AD9600. for applications where snr is a key parameter, differential double-balun coupling is the recommended input configuration. an example is shown in figure 49 . an alternative to using a transformer-coupled input at frequencies in the second nyquist zone is to use the ad8352 differential driver. an example is shown in figure 50 . see the ad8352 data sheet for more information. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and source impedance and may need to be reduced or removed. table 10 lists the recommended values to set the rc network. however, the actual values are dependent on the input signal; therefore, table 10 should only be used as a starting guide. table 10. example rc network freuency range (mz) r series (, each) c differential (pf) 0 to 70 33 15 70 to 200 33 5 200 to 300 15 5 >300 15 open single-ended input configuration a single-ended input can provide adequate performance in cost-sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common- mode swing. if the source impedances on each input are matched, there should be little effect on snr performance. figure 48 details a typical single-ended input configuration. 2v p-p r r c 49.9 ? 0.1f 10f 10f 0.1f avdd 1k? 1k? 1k ? 1k ? adc AD9600 avdd vin+ vin? 06909-018 figure 48. single-ended input configuration AD9600 r 0.1f 0.1f 2v p-p vin+ vin? cml c r 0.1f s 0.1f 25 ? 25 ? s p a p 06909-228 figure 49. differential double-balun input configuration AD9600 ad8352 0 ? r 0 ? c d r d r g 0.1f 0.1f 0.1f vin+ vin? cml c 0.1f 16 1 2 3 4 5 11 r 0.1f 0.1f 10 14 0.1f 8, 13 v cc 200 ? 200 ? analog input analog input 06909-270 figure 50. differential input configuration using the ad8352 AD9600 rev. 0 | page 24 of 72 voltage reference a stable and accurate voltage reference is built into the AD9600. the input range can be adjusted by varying the reference voltage applied to the AD9600, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. the various reference modes are summarized in this section. the reference decoupling section describes the best pcb layout practices for the reference. internal reference connection a comparator within the AD9600 detects the potential at the sense pin and configures the reference into four possible modes, which are summarized in tabl e 11 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 51 ), setting vref to 1.0 v. connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected external to the chip as shown in figure 52 , the switch again selects the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as ? ? ? ? ? ? += 15. 0 the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. vref sense 0.5v AD9600 select logic 0.1f 1f vin ? a/vin ? b vin + a/vin + b adc core 06909-019 figure 51. internal reference configuration sense vref 0.5v AD9600 select logic 0.1f 1 f vin ? a/vin ? b vin + a/vin + b adc core r2 r1 06909-020 figure 52. programmable reference configuration if the internal reference of the AD9600 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 53 depicts how the internal reference voltage is affected by loading. 0 ?1.25 02 load current (ma) reference voltage error (%) . 0 ?0.25 ?0.50 ?0.75 ?1.00 0.5 1.0 1.5 vref = 0.5v vref = 1.0v 0 6909-280 figure 53. vref accuracy vs. load table 11. reference configuration summary selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference internal fixed reference vref 0.5 1.0 programmable reference 0.2 v to vref ? ? ? ? ? ? + 15.0 (see figure 52 ) 2 vref internal fixed reference agnd to 0.2 v 1.0 2.0 AD9600 rev. 0 | page 25 of 72 external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve the thermal drift characteristics. figure 54 shows the typical drift characteristics of the internal reference in 1.0 v mode. 2.5 ?2.5 ?40 temperature (c) reference voltage error (mv) 2.0 1.5 1.0 0 ?0.5 ?1.0 ?1.5 ?2.0 ?200 20406080 06909-299 figure 54. typical vref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 6 k load (see figure 15 ). the internal buffer generates the positive and negative full-scale references for the adc core. therefore, the external reference must be limited to a maximum of 1.0 v. clock input considerations for optimum performance, the AD9600 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 55 ) and require no external bias. 1.2v clk+ avdd clk? 2pf 2pf 06909-023 figure 55. equivalent clock input circuit clock input options the AD9600 has a very flexible clock input structure. the clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, the jitter of the clock source is of the most concern, as described in the jitter considerations section. figure 56 and figure 57 show preferred methods for clocking the AD9600 (at clock rates of up to 625 mhz). a low jitter clock source is converted from a single-ended signal to a differential signal using either an rf balun or an rf transformer. the rf balun configuration is recommended for clock frequencies between 125 mhz and 625 mhz, and the rf transformer is recommended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the secondary transformer or balun limit clock excursions into the AD9600 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9600 while preserving the fast rise and fall times of the signal that are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clk+ 50? 100? clk? clk+ adc AD9600 mini-circuits ? adt1-1wt, 1:1z xfmr 06909-024 figure 56. transformer-coupled differential clock (up to 200 mhz) 0.1f 0.1f 1nf clk+ 1nf 50? clk? clk+ adc AD9600 schottky diodes: hsms2822 06909-057 figure 57. balun-coupled differential clock (up to 625 mhz) if a low jitter clock source is not available, another option is to ac-couple a differential pecl signal to the sample clock input pins as shown in figure 58 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offers excellent jitter performance. 100? 0.1f 0.1f 0.1f 0.1f 240? 240? pecl driver a d9510/ad9511/ad9512/ ad9513/ad9514/ad9515 50k? 50k? clk? clk+ adc AD9600 c lk+ clk? 06909-025 figure 58. differential pecl sample clock (up to 150 msps) a third option is to ac-couple a differential lvds signal to the sample clock input pins as shown in figure 59 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k ? lvds driver 50k ? clk? clk+ clk? clk+ adc AD9600 ad9510/ad9511/ad9512/ ad9513/ad9514/ad9515 06909-026 figure 59. differential lvds sample clock (up to 150 msps) AD9600 rev. 0 | page 26 of 72 in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 60 ). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages of up to 3.6 v and therefore offers several selections for the drive logic voltage. optional 100 ? 0.1f 0.1f 0.1f 39k? cmos driver 50? clk? clk+ adc AD9600 vcc 1k? 1k? clk+ ad9510/ad9511/ad9512/ ad9513/ad9514/ad9515 06909-027 figure 60. single-ended 1.8 v cmos sample clock (up to 150 msps) optional 100? 0.1f 0.1f 0.1f vcc cmos driver 50 ? clk? clk+ adc AD9600 1k? 1k? c lk+ ad9510/ad9511/ad9512/ ad9513/ad9514/ad9515 06909-028 figure 61 single-ended 3.3 v cmos sample clock (up to 150 msps) input clock divider the AD9600 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. if a divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled. the AD9600 clock divider can be synchronized by using the external sync input. bit 1 and bit 2 of register 0x100 allow the clock divider to be resynchronized either on every sync signal or on only the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchronization feature allows aligning the clock dividers of multiple devices to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9600 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (or falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9600. when the sdio/dcs pin functions as dcs, noise and distortion performance are nearly flat for a wide range of duty cycles, as shown in figure 43 . jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz nominally. the loop has a time constant associated with it that needs to be considered if the clock rate may change dynamically. this requires a wait time of 1.5 s to 5 s after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during this time, the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty clock stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calculated as jin tf snr u s 2log20 in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter. if undersampling applications are particularly sensitive to jitter (see figure 62 ). 06909-162 65 60 55 50 45 1 10 100 1000 snr (dbc) input frequency (mhz) 3.00ps 0.05ps 0.20ps 0.5ps 1.0ps 1.50ps 2.00ps 2.50ps measured figure 62. snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9600. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock during the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs. AD9600 rev. 0 | page 27 of 72 power dissipation and standby mode as shown in figure 63 , the power dissipated by the AD9600 is proportional to its sample rate. in cmos output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current (i drvdd ) can be calculated as nfcvi clk load drvdd drvdd = where n is the number of output bits (22 in the case of AD9600 with the fast detect output pins disabled). this maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the nyquist frequency, f clk /2. in practice, the drvdd current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. reducing the capacitive load presented to the output drivers can minimize digital power consumption. the data in figure 63 was taken with the same operating conditions as the typical performance characteristics , with a 5 pf load on each output driver. total power (w) supply current (a) encode (msps) 0 0.1 0.2 0.3 0.4 0.5 i avdd i dvdd i drvdd 0.25 0 0.50 0.75 1.00 1.25 0 255075100125150 total power 06909-038 figure 63. AD9600-150 power and current vs. sample rate total power (w) supply current (a) encode (msps) 0 0.1 0.2 0.3 0.4 0.5 i avdd i dvdd i drvdd 0.25 0 0.50 0.75 1.00 1.25 0 25 50 75 100 125 total power 06909-039 figure 64. AD9600-125 power and current vs. sample rate total power (w) supply current (a) encode (msps) 0 100 75 50 25 0 0.25 0.50 0.75 1.00 0 0.1 0.2 0.3 0.4 06909-999 i avdd i dvdd i drvdd total power figure 65. AD9600-105 power and current vs. sample rate by asserting the pdwn mode (either through the spi port or by asserting the pdwn pin high), the AD9600 is placed into power-down mode. in this state, the adc typically dissipates 2.5 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the AD9600 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. in power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power-down mode and must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in power-down mode: shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc into power-down or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map register description section for more details. digital outputs the AD9600 output drivers can be configured to interface with 1.8 v to 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. in cmos output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies and may affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. the output data format can be selected for either offset binary or twos complement by setting the sclk/dfs pin when operating in the external pin mode (see table 12 ). as detailed in the memory map register description section, the data format can be selected for offset binary, twos complement, or gray code when using the spi control. AD9600 rev. 0 | page 28 of 72 table 12. sclk/dfs mode selection (external pin mode) voltage at pin sclk/dfs sdio/dcs agnd (default) binary dcs disabled avdd twos complement dcs enabled digital output enable function (oeb) the AD9600 has a flexible three-state ability for the digital output pins the three-state mode can be enabled by using the smi sdo/oeb pin or the spi interface if the smi sdo/oeb pin is low the output data drivers are enabled if the smi sdo/oeb pin is high the output data drivers are placed into a high impedance state this output enable function is not intended for rapid access to the data bus note that oeb is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage when the device uses the spi interface each channels data and fast detect output pins can be independently three-stated by using the output enable bar bit in register 0x14 timing the AD9600 provides latched data with a pipeline delay of 12 clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. the length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9600. these transients can degrade the dynamic performance of the converter. the lowest typical conversion rate of the AD9600 is typically 10 msps. at clock rates below 10 msps, dynamic performance may degrade. data clock output (dco) the AD9600 provides two data clock output (dco) signals intended for capturing the data in an external register the data outputs are valid on the rising edge of dco unless the polarity has been changed via the spi see the timing diagrams shown in figure 2 and figure 3 for more information table 13. output data format input (v) condition (v) binary output mode twos complement mode overrange (vin+ ) ? (vin? ) < ?vref ? 0.5 lsb 00 0000 0000 10 0000 0000 1 (vin+ ) ? (vin? ) = Cvref 00 0000 0000 10 0000 0000 0 (vin+ ) ? (vin? ) = 0 10 0000 0000 00 0000 0000 0 (vin+ ) ? (vin? ) = +vref ? 1.0 lsb 11 1111 1111 01 1111 1111 0 (vin+ ) ? (vin? ) > +vref ? 0.5 lsb 11 1111 1111 01 1111 1111 1 AD9600 rev. 0 | page 29 of 72 adc overrange and gain control in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overflow indicator provides after-the-fact infor- mation on the state of the analog input that is of limited usefulness. therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. in addition, because input signals can have significant slew rates, latency of this function is of major concern. highly pipelined converters can have significant latency. a good compromise is to use the output bits from the first stage of the adc for this function. latency for these output bits is very low, and overall resolution is not highly significant. peak input signals are typically between full scale and 6 db to 10 db below full scale. a 3-bit or 4-bit output provides adequate range and resolution for this function. via the spi port, the user can provide a threshold above which an overrange output would be active. as long as the signal is below that threshold, the output should remain low. the fast detect output pins can also be programmed via the spi port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature. in this mode, all 12 bits of the converter are examined in the traditional manner, and the output is high for the condition normally defined as overflow. in either mode, the magnitude of the data is considered in the calculation of the condition (but the sign of the data is not considered). the threshold detection responds identically to positive and negative signals outside the desired magnitude range. fast detect overview the AD9600 contains circuitry to facilitate fast overrange detec- tion, allowing very flexible external gain control implementations. each adc has four fast detect output pins that are used to output information about the current state of the adc input level. the function of these pins is programmable via the fast detect mode select bits and the fast detect enable bit in register 0x104, allowing range information to be output from several points in the internal datapath. these pins can also be set up to indicate the presence of overrange or underrange conditions, according to programmable threshold levels. table 14 shows the six configurations available for the fast detect pins. table 14. fast detect mode select bits settings information presented on fast detect (fd) pins of each adc 1, 2 fast detect mode select bits (register 0x104 [3:1]) fd [3] fd [2] fd [1] fd [0] 000 adc fast magnitude (see table 15 ) 001 adc fast magnitude (see table 16 ) or 010 adc fast magnitude (see table 17 ) or f_lt 011 adc fast magnitude (see table 17 ) c_ut f_lt 100 or c_ut f_ut f_lt 101 or f_ut ig dg 1 the fast detect pins are fd0a/fd0b to fd9a/fd9b for the cmos mode configuration and fd0+/fd0? to fd9+/fd9? for the lvds mode configuration. 2 see the adc overrange (or) and gain switching sections for more information about or, c_ut, f_ut, f_lt, ig, and dg. adc fast magnitude when the fast detect output pins are configured to output the adc fast magnitude (that is, when the fast detect mode select bits are set to 0b000), the information presented is the adc level from an early converter stage with only a two-clock-cycle latency (when in cmos output mode). using the fast detect output pins in this configuration provides the earliest possible level indication information. because this information is provided early in the datapath, there is a significant uncertainty in the level indicated. the nominal levels, along with the uncertainty indicated by the adc fast magnitude, are shown in table 15 . table 15. adc fast magnitude nominal levels with fast detect mode select bits = 000 adc fast magnitude on fd [3:0] pins nominal input magnitude below fs (db) nominal input magnitude uncertainty (db) 0000 AD9600 rev. 0 | page 30 of 72 when the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. in these modes, the fast detect output pins have a latency of six clock cycles. table 16 shows the corresponding adc input levels when the fast detect mode select bits are set to 0b001 (that is, when adc fast magnitude is presented on the fd [3:1] pins). table 16. adc fast magnitude nominal levels with fast detect mode select bits = 001 adc fast magnitude on fd [3:1] pins nominal input magnitude below fs (db) nominal input magnitude uncertainty (db) 000 AD9600 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. this circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. fast detect mode select bit = 010 through fast detect mode select bit = 101 support various combinations of the gain switching options. one such use is to detect when an adc is about to reach full scale with a particular input condition. the result is to provide an indicator that can be used to quickly insert an attenuator that prevents adc overdrive. coarse upper threshold (c_ut) the coarse upper threshold indicator is asserted if the adc fast magnitude input level is greater than the level programmed in the coarse upper threshold register at address 0x105 [2:0]. the coarse upper threshold output is output two clock cycles after the level is exceeded at the input and therefore provides a fast indication of the input signal level. the coarse upper threshold levels are shown in table 18 . this indicator remains asserted for a minimum of two adc clock cycles or until the signal drops below the threshold level. table 18. coarse upper threshold levels coarse upper threshold (register 0x105 [2:0]) c_ut is active when signal magnitude below fs is greater than (db) 000 AD9600 rev. 0 | page 31 of 72 increment gain (ig) and decrement gain (dg) the increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. the decrement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (address 0x105). the increment gain indicator, similarly, corresponds with the fine lower threshold bits, except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. this dwell time is set by the 16-bit increase gain dwell time register (address 0x10a and address 0x10b) and is in units of adc input clock cycles ranging from 1 to 65,535. the fine lower threshold register is a 13-bit register that is compared with the magnitude at the output of the adc. this comparison is subject to the adc clock latency but allows a finer, more accurate comparison. the fine threshold magnitude is defined in equation 1 (see the fine upper threshold (f_ut) section). the decrement gain output is influenced by the fast detect output pins, which provide a fast indication of potential overrange conditions. assertion of the increment gain indicator is based on the comparison at the output of the adc, requiring the input magnitude to remain below an accurate, programmable level for a predefined period before signaling external circuitry to increase the gain. the operation of the ig and dg indicators is shown in figure 66 . 0 6909-097 upper threshold (coarse or fine) fine lower threshold ig dg f_lt c_ut or f_ut* dwell time timer reset by rise above f_lt timer completes before signal rises above f_lt note: outputs follow the instantaneous signal level and not the envelope but are guaranteed active for a minimum of two adc clock cycles. *c_ut and f_ut differ only in accuracy and latency. dwell time figure 66. threshold settings fo r c_ut, f_ut, f_lt, ig, and dg AD9600 rev. 0 | page 32 of 72 signal monitor the signal monitoring block provides additional information about the signal being digitized by the adc. the signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular threshold. together, these functions can be used to gain insight into the signal characteristics and to estimate the peak/average ratio or even the shape of the complementary cumulative distribution function (ccdf) curve of the input signal. this information can be used to drive an agc loop to optimize the range of the adc in the presence of real-world signals. the signal monitor result values can be obtained from the part by reading back register 0x116 to register 0x11b, using the spi port or the signal monitor sport output. the output contents of the spi-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register (address 0x112). both adc channels must be configured for the same signal monitor mode. separate spi-accessible, 20-bit signal monitor result (smr) registers (address 0x116 to address 0x11b) are provided for each adc channel. any combination of the signal monitor functions can also be output to the user via the serial sport interface. these outputs are enabled using the peak detector output enable, rms magnitude output enable, and threshold crossing output enable bits in the signal monitor sport control register (address 0x111). for each of the signal monitor measurements, a programmable signal monitor period register (smpr) controls the duration of the measurement. this period is programmed as the number of input clock cycles in the 24-bit signal monitor period register located at address 0x113, address 0x114, and address 0x115. this register can be programmed with a period from 128 samples to 16.78 (2 24 ) million samples. because the dc offset of the adc can be significantly larger than the signal of interest (affecting the results from the signal monitor), a dc correction circuit is included as part of the signal monitor block to null the dc offset before measuring the power. peak detector mode the magnitude of the input port signal is monitored over a programmable period (determined by smpr) to give the peak value detected. this function is enabled by programming a logic 1 in the signal monitor mode bits of the signal monitor control register (address 0x112) or by setting the peak detector output enable bit in the signal monitor sport control register (address 0x111). the 24-bit smpr must be programmed before activating this mode. after enabling this mode, the value in the smpr is loaded into a monitor period timer and the countdown is started. the magni- tude of the input signal is compared with the value in the internal peak level holding register (not accessible to the user), and the greater of the two values is updated as the current peak level. the initial value in the peak level holding register is set to the current adc input signal magnitude, and the comparison continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the 13-bit value in the peak level holding register is transferred to the signal monitor holding register (not accessible to the user) and can be read through the spi port or output through the sport serial interface. the monitor period timer is reloaded with the value in the smpr, and the countdown is restarted. in addition, the value in the peak level holding register is reset to the magnitude of the first input sample, and the previously explained comparison and update procedure continues. figure 67 is a block diagram of the peak detector logic. the smr register contains the absolute magnitude of the peak detected by the peak detector logic. signal monitor holding register (smr)* magnitude storage register* compare a>b to memory map/sport from memory map from input ports load clear load load is count = 1? down counter signal monitor period register * these are internal registers. they are not in the register map and cannot be accessed by users. 0 6909-044 figure 67. adc input peak detector block diagram rms/ms magnitude mode in this mode, the root-mean-square (rms) or mean-square (ms) magnitude of the input port signal is integrated (by adding an accumulator) over a programmable period (determined by smpr) to give the rms or ms magnitude of the input signal. this mode is set by programming logic 0 in the signal monitor mode bits of the signal monitor control register (address 0x112) or by setting the rms magnitude output enable bit in the signal monitor sport control register (address 0x111). the 24-bit smpr, representing the period over which integration is performed, must be programmed before activating this mode. after enabling the rms/ms magnitude mode, the value in the smpr is loaded into a monitor period timer, and the countdown is started immediately. each input sample is converted to floating-point format and squared. it is then converted to an 11-bit fixed-point format and added to the contents of the 24-bit accumulator. the integration continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the square root of the value in the accumulator is taken and transferred (after some formatting) to the signal monitor holding register, which can be read through the spi port or output through the sport serial port. the monitor period timer is reloaded with the value in the smpr, and the countdown is restarted. in addition, AD9600 rev. 0 | page 33 of 72 the value of the accumulator is reset to the first input sample signal power, and the accumulation continues with the subsequent input samples. figure 68 illustrates the rms magnitude monitoring logic. 06909-092 signal monitor holding register (smr)* accumulator to memory map/sport from memory map from input ports load clear load is count = 1? down counter signal monitor period register *this is an internal register. it is not in the register map and cannot be acc essed by users. figure 68. adc input rms magnitude monitoring block diagram for rms magnitude mode, the value in the signal monitor result (smr) register is a 20-bit fixed-point number. the following equation can be used to determine the rms magnitude in decibels full scale (dbfs) from the mag value in the register: rms magnitude = 20 log [] ? ? ? ? ? ? ? ? ? ? ? ? ? )(log 20 2 2 log10 2 smp ceil smp mag where if the signal monitor period (smp) is a power of 2, the second term in the equation becomes 0. for ms magnitude mode, the value in the smr is a 20-bit fixed- point number. the following equation can be used to determine the ms magnitude in decibels full scale (dbfs) from the mag value in the register: ms magnitude = 10 log [] ? ? ? ? ? ? ? ? ? ? ? ? ? )(log 20 2 2 log10 2 smp ceil smp mag where if the smp is a power of 2, the second term in the equation becomes 0. threshold crossing mode in the threshold crossing mode of operation, the magnitude of the input port signal is monitored over a programmable period (determined by smpr) to count the number of times it crosses a certain programmable threshold value. this mode is set by programming logic 1x (where x is a dont care bit) in the signal monitor mode bits of the signal monitor control register (address 0x112) or by setting the threshold crossing output enable bit in the signal monitor sport control register (address 0x111). before activating this mode, the user needs to program the 24-bit signal monitor period register (address 0x113 to address 0x115) and the 13-bit fine upper threshold register (address 0x106 and address 0x107) for each individual input port. the same fine upper threshold register is used for both signal monitoring and gain control (see the adc overrange and gain control section). after entering this mode, the value in the smpr is loaded into a monitor period timer and the countdown is started. the magnitude of the input signal is compared with the previously programmed fine upper threshold register on each input clock cycle. if the input signal has a magnitude greater than the value set in the fine upper threshold register, the value in the internal count register (not accessible to the user) is incremented by 1. the initial value of the internal count register is set to 0. the comparison and incrementing of this value continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the value in the internal count register is transferred to the signal monitor holding register (not accessible to the user), which can be read through the spi port or output through the sport serial port. the monitor period timer is reloaded with the value in the smpr, and the countdown is restarted. the internal count register is also cleared to a value of 0. figure 69 illustrates the threshold crossing logic. the value in the smr register is the number of samples that have a magnitude greater than the fine upper threshold register. 06909-046 signal monitor holding register (smr)* compare a > b compare a > b to memory map/sport from memory map from memory map from input ports load clear load is count = 1? down counter signal monitor period register b a *this is an internal register. it is not in the register map and cannot be accessed by users. fine upper threshold register figure 69. adc input threshold crossing block diagram additional control bits for additional flexibility in the signal monitoring process, two control bits are provided in the signal monitor control register (address 0x112). they are the signal monitor enable bit and the complex power calculation mode enable bit. signal monitor enable bit the signal monitor enable bit, located in bit 0 of register 0x112, enables operation of the signal monitor block. if the signal monitor function is not needed in a particular application, this bit should be cleared (default) to conserve power. complex power calculation mode enable bit when this bit is set, the part assumes that channel a is digitizing the i data and channel b is digitizing the q data for a complex input signal (or vice versa). in this mode, the power reported is equal to 22 qi + this result is presented in the signal monitor dc value channel a register (address 0x10d and address 0x10e) if the signal monitor mode bits are set to 00. the signal monitor dc value channel b register (address 0x10f and address 0x110) continues to compute the channel b value. AD9600 rev. 0 | page 34 of 72 dc correction enable bits dc correction setting bit 0 (the dc correction for sm enable bit) of register 0x10c enables the dc correction for use in the signal monitor calculations. setting bit 1 (the dc correction for signal path enable bit) of register 0x10c enables the calculated dc correction value to be added to the output data signal path. because the dc offset of the adc may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. the dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the adc is digitizing a time-varying signal with significant dc content, such as gsm. signal monitor sport output dc correction bandwidth the sport is a serial interface with three output pins: smi sclk (sport clock), smi sdfs (sport frame sync), and smi sdo (sport data). the sport is the master and drives all three sport output pins on the chip. the dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 hz and 1.2 khz at 125 msps). the bandwidth is controlled by writing the 4-bit dc correction bandwidth register located at register 0x10c, bits [5:2]. smi sclk the following equation can be used to compute the bandwidth value for the dc correction circuit: the data and frame sync are driven on the positive edge of the smi sclk. the smi sclk has three possible baud rates: 1/2, 1/4, or 1/8 the adc clock rate, based on the sport controls. in addition, by using the sport smi sclk sleep bit, the smi sclk can be gated to remain low when the signal monitor block is not sending any data. using this bit to disable the smi sclk when it is not needed can reduce coupling er rors in the return signal path. doing so, however, has the disadvantage of spreading the frequency content of the clock; if desired, the smi sclk can be left enabled to ease frequency planning. = ?? 2 2__ 14 clk k f bwcorrdc where: k is the 4-bit value programmed in register 0x10c, bits [5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the AD9600 adc sample rate in hertz. dc correction readback smi sdfs the current dc correction value can be read back in register 0x10d and register 0x10e for channel a and register 0x10f and register 0x110 for channel b. the dc correction value is a 10-bit value that can span the entire input range of the adc. the smi sdfs is the serial data frame sync. it defines the start of a frame. one sport frame includes data from both datapaths. the data from datapath a is sent just after the frame sync, followed by data from datapath b. dc correction freeze smi sdo setting the dc correction freeze bit (bit 6 of register 0x10c) halts the dc correction at its current state and continues to use the last updated value as the dc correction value. clearing this bit restarts dc correction and adds the currently calculated value to the data. the smi sdo is the serial data output of the block. the data is sent msb first on the first positive edge after the smi sdfs. each data output block includes one or more rms magnitude value, peak level value, and threshold crossing value from each datapath in the stated order. if enabled, the data is sent, rms first, followed by the peak value and the threshold crossing value, as shown in figure 70 . 20 cycles 16 cycles 16 cycles 20 cycles 16 cycles 16 cycles smi sdfs msb msb rms/ms ch a pk ch a pk ch b thr ch b rms/ms ch b rms/ms ch a lsb lsb thr ch a smi sdo/oeb smi sclk/pdwn gated, based on control 06909-094 figure 70. signal monitor sport output ti ming (rms, peak, and threshold enabled) 20 cycles 16 cycles 20 cycles 16 cycles s mi sclk/pdwn smi sdfs smi sdo/oeb msb msb rms/ms ch a rms/ms ch a lsb thr ch a rms/ms ch b lsb thr ch b gated, based on control 0 6909-095 figure 71. signal monitor sport output timing (rms and threshold enabled) AD9600 rev. 0 | page 35 of 72 built-in self-test (bist) and output test the AD9600 includes built-in test fe atures to enable verification of the integrity of each channel as well as to facilitate board level debugging. a bist feature is included that verifies the integrity of the digital datapath of the AD9600. various output test options are also provided to place predictable values on the outputs of the AD9600. built-in self-test (bist) the bist is a thorough test of the digital portion of the selected AD9600 signal path. when enabled, the test runs from an internal pseudorandom noise (pn) source through the digital datapath, starting at the adc block output. the bist sequence runs for 512 cycles and then stops. the bist signature value for channel a or channel b is placed in register 0x24 and register 0x25. if one channel is chosen, its bist signature is written to the two registers. if both channels are chosen, the results of the two channels are xored and placed in the bist signature registers. the outputs are not disconnected during this test; therefore, the pn sequence can be observed as it runs. the pn sequence can be continued from its last value or started from the beginning, based on the value programmed in bit 2 of register 0x0e. the bist signature result varies depending on the channel configuration. output test modes the output test options are shown in tabl e 22 . when an output test mode is enabled, the analog section of the adc is discon- nected from the digital back end blocks, and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the seed value for the pn sequence tests can be forced by setting bit 4 or bit 5 of the test mode register (address 0x0d) to hold the generator in reset mode. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see an-877 application note , interfacing to high speed adcs via spi . AD9600 rev. 0 | page 36 of 72 channel/chip synchronization the AD9600 has a sync input that offers the user flexible synchronization options for synchronizing the internal blocks. the clock divider sync feature is useful to guarantee synchronized sample clocks across multiple adcs. the signal monitor block can also be synchronized using the sync input, allowing properties of the input signal to be measured during a specific period. the input clock divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence. the signal monitor block is synchronized on every sync input signal. the sync input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the sync input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in tabl e 5. the sync input should be driven using a single-ended cmos-type signal. AD9600 rev. 0 | page 37 of 72 serial port interface (spi) the AD9600 spi allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. this may provide the user with additional flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for detailed operational information, see an-877 application note , interfacing to high speed adcs via spi . configuration using the spi there are three pins that define the spi: sclk, sdio, and csb (see tabl e 19 ). the sclk pin is used to synchronize the read and write data presented from and to the adc. the sdio pin is a dual-purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb pin is an active- low control that enables or disables the read and write cycles. table 19. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active-low control that gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing. an example of the serial timing and its definitions can be found in figure 72 and tabl e 5. other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. this mode turns on any secondary functions of the spi pin. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. w0 and w1 represent the number of data bytes to transfer for either a read or a write. the value represented by w1:w0 + 1 is the number of bytes to transfer. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether a read command or a write command is issued. this allows the sdio pin to change direction from an input to an output. in addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb-first mode or lsb-first mode. msb-first mode is the default on power-up and can be changed via the spi port configuration register (addr ess 0x00). for more information about this and other features, see an-877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 19 constitute the physical interface between the user programming device and the serial port of the AD9600. the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in an-812 application note , microcontroller- based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9600 to keep these signals from transitioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to avdd or ground during device power-on, they are associated with a specific function. the theory of operation section describes the strappable functions supported on the AD9600. AD9600 rev. 0 | page 38 of 72 configuration without the spi in applications that do not interface to the spi control registers, the sdio/dcs pin, the sclk/dfs pin, the smi sdo/oeb pin, and the smi sclk/pdwn pin serve as standalone cmos- compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. in this mode, the csb chip select should be connected to avdd, which disables the serial port interface. table 20. mode selection pin external voltage configuration avdd (default) duty cycle stabilizer enabled sdio/dcs agnd duty cycle stabilizer disabled avdd twos complement enabled sclk/dfs agnd (default) offset binary enabled avdd outputs in high impedance smi sdo/oeb agnd (default) outputs enabled avdd chip in power-down or standby smi sclk/pdwn agnd (default) normal operation spi accessible features brief descriptions of the general features available on many analog devices, inc., high speed adcs, including the AD9600, that are accessible via the spi are included in tabl e 21 . these features are described in detail in the an-877 application note , interfacing to high speed adcs via spi . the AD9600 part-specific features are described in the memory map register description section. table 21. features accessible using the spi feature name description modes allows the user to set either the power-down mode or the standby mode clock allows the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set the test modes to have known data on the output bits output mode allows the user to set up the outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 06909-049 figure 72. serial port interface timing diagram AD9600 rev. 0 | page 39 of 72 memory map reading the memory map table each row in the memory map registers table ( table 22 ) has eight bit locations. the memory map is divided into four sections: the chip configuration registers (address 0x00 to address 0x02), the channel index and transfer registers (address 0x05 and address 0xff), the adc functions registers (address 0x08 to address 0x25), and the digital feature control registers (address 0x100 to address 0x11b). the leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. the (msb) bit 7 column is the start of the default hexadecimal value given. for example, address 0x18, the vref select register, has a default value of 0xc0, meaning that bit 7 = 1, bit 6 = 1, and the remaining bits are 0s. this setting is the default reference selection setting. the default value uses a 2.0 v peak-to-peak reference. for more information on this function and others, see the an-877 application note , interfacing to high speed adcs via spi. this application note details the functions controlled by register 0x00 to register 0xff. the remaining registers (from register 0x100 to register 0x11b) are documented in the memory map register description section. open locations all address and bit locations that are not included in tabl e 22 are currently not supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values when the AD9600 comes out of a reset, critical registers are loaded with default values. the default values for the registers are given in the memory map registers table ( table 22 ). logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x18 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simulta- neously when the transfer bit (bit 0 of register 0xff) is set. the internal update takes place when the transfer bit is set, and the bit autoclears. channel-specific registers some channel setup functions, such as the signal monitor thresholds, can be individually programmed for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers are designated as local registers in tabl e 22 and can be accessed by setting the appropriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel a. on the other hand, registers that are designated as global registers in tabl e 22 affect the entire part or the channel features for which independent settings are not allowed between the channels. the settings in register 0x05 do not affect the global registers. AD9600 rev. 0 | page 40 of 72 memory map all address and bit locations that are not included in tabl e 22 are currently not supported for this device. table 22. memory map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 spi port configuration (global) 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so that lsb- or msb-first mode is set correctly, regardless of shift mode. 0x01 chip id (global) 8-bit chip id [7:0] (AD9600 = 0x12) (default) 0x12 read only read only. 0x02 chip grade (global) open open speed grade id 00 = 150 msps 01 = 125 msps 10 = 105 msps 11 = 80 msps open open open open read only speed grade id used to differentiate devices. channel index and transfer registers 0x05 channel index open open open open open open data channel b (default) data channel a (default) 0x03 bits are set to determine which on-chip device receives the next write command; applies to local registers. 0xff transfer open open open ope n open open open transfer 0x00 synchronously transfers data from the master shift register to the slave. adc functions registers 0x08 power modes open open external power- down pin function (global) 0 = power- down 1 = standby open open open internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation 0x00 determines various generic modes of chip operation. 0x09 global clock (global) open open open ope n open open open duty cycle stabilizer (default) 0x01 0x0b clock divide (global) open open open open open clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 automatically cause the duty cycle stabilizer to become active. 0x0d test mode (local) open open reset pn23 gen reset pn9 gen open output test mode 000 = off (default) 001 = midscale short 010 = positive fs 011 = negative fs 100 = alternating checkerboard 101 = pn 23 sequence 110 = pn 9 sequence 111 = one/zero word toggle 0x00 when this register is set, the test data is placed on the output pins in place of normal data. AD9600 rev. 0 | page 41 of 72 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0e bist enable (local) open open open open open reset bist sequence open bist enable 0x00 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to ?32 (twos complement format) 0x00 0x14 output mode drive strength 0 v to 3.3 v cmos or ansi lvds: 1 v to 1.8 v cmos or reduced: lvds (global) output type 0 = cmos 1 = lvds (global) open output enable bar (local) open output invert (local) 00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary (local) 0x00 configures the outputs and the format of the data. 0x16 clock phase control (global) invert dco clock open open open open in put clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 allows selection of clock delays into the input clock divider. 0x17 dco output delay (global) open open open dco clock delay (delay = 2500 ps register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps 11110 = 2419 ps 11111 = 2500 ps 0x00 0x18 vref select (global) reference voltage selection 00 = 1.25 v p-p 01 = 1.5 v p-p 10 = 1.75 v p-p 11 = 2.0 v p-p (default) open open open open open open 0xc0 0x24 bist signature lsb (local) bist signature [7:0] 0x00 read only. 0x25 bist signature msb (local) bist signature [15:8] 0x00 read only. digital feature control registers 0x100 sync control (global) signal monitor sync enable open open open open clock divider next sync only clock divider sync enable master sync enable 0x00 0x104 fast detect control (local) open open open open fast dete ct mode select [2:0] fast detect enable 0x00 0x105 coarse upper threshold (local) open open open open open coarse upper threshold [2:0] 0x00 0x106 fine upper threshold register 0 (local) fine upper threshold [7:0] 0x00 0x107 fine upper threshold register 1 (local) open open open fine upper threshold [12:8] 0x00 0x108 fine lower threshold register 0 (local) fine lower threshold [7:0] 0x00 0x109 fine lower threshold register 1 (local) open open open fine lower threshold [12:8] 0x00 AD9600 rev. 0 | page 42 of 72 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x10a increase gain dwell time register 0 (local) increase gain dwell time [7:0] 0x00 in adc clock cycles. 0x10b increase gain dwell time register 1 (local) increase gain dwell time [15:8] 0x00 in adc clock cycles. 0x10c signal monitor dc correction control (global) open dc correction freeze dc correction bandwidth [3:0] dc correction for signal path enable dc correction for signal monitor enable 0x00 0x10d signal monitor dc value channel a register 0 (global) dc value channel a [7:0] read only. 0x10e signal monitor dc value channel a register 1 (global) open open dc value channel a [13:8] read only. 0x10f signal monitor dc value channel b register 0 (global) dc value channel b [7:0] read only. 0x110 signal monitor dc value channel b register 1 (global) open open dc value channel a [13:8] read only 0x111 signal monitor sport control (global) open rms/ms magnitude output enable peak detector output enable threshold crossing output enable sport smi sclk divide 00 = undefined 01 = divide by 2 10 = divide by 4 11 = divide by 8 sport smi sclk sleep signal monitor sport output enable 0x04 0x112 signal monitor control (global) complex power calculation mode enable open open open signal monitor rms/ms select 0 = rms 1 = ms signal monitor mode 00 = rms/ms magnitude 01 = peak power 10 = threshold crossing 11 = threshold crossing signal monitor enable 0x00 0x113 signal monitor period register 0 (global) signal monitor period [7:0] 0x80 in adc clock cycles. 0x114 signal monitor period register 1 (global) signal monitor pe riod [15:8] 0x00 in adc clock cycles. 0x115 signal monitor period register 2 (global) signal monitor pe riod [23:16] 0x00 in adc clock cycles. 0x116 signal monitor result channel a register 0 (global) signal monitor result channel a [7:0] read only. 0x117 signal monitor result channel a register 1 (global) signal monitor result channel a [15:8] read only. AD9600 rev. 0 | page 43 of 72 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x118 signal monitor result channel a register 2 (global) open open open open signal monitor value channel a [19:16] read only. 0x119 signal monitor result channel b register 0 (global) signal monitor result channel b [7:0] read only. 0x11a signal monitor result channel b register 1 (global) signal monitor result channel b [15:8] read only. 0x11b signal monitor result channel b register 2 (global) open open open open signal monitor result channel b [19:16] read only. memory map register description for information about functions controlled in register 0x00 to register 0xff, see application note an-877, interfacing to high speed adcs via spi . sync control (register 0x100) bit 7signal monitor sync enable bit 7 enables the sync pulse from the external sync input to the signal monitor block. the sync signal is passed when both bit 7 and bit 0 are high. this is continuous sync mode. bits [6:3]reserved bit 2clock divider next sync only if the master sync enable bit (address 0x100 [0]) is high and the clock divider sync enable bit (address 0x100 [1]) is high, the clock divider next sync only bit (address 0x100 [2]) allows the clock divider to sync to the first sync pulse it receives and ignore the rest. the clock divider sync enable bit (address 0x100 [1]) resets after it syncs. bit 1clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is passed when both bit 1 and bit 0 are high. this is continuous sync mode. bit 0master sync enable bit 0 must be high to enable the sync functions. fast detect control (register 0x104) bits [7:4]reserved bits [3:1]fast detect mode select these bits set the mode of the fast detect output pins according to tabl e 14 . bit 0fast detect enable bit 0 is used to enable the fast detect output pins. when the fast detect output pins are disabled, the outputs go into a high impedance state. in lvds mode, when the fast detect output pins are interleaved, the outputs go high-z only if both channels are turned off (power-down/standby/output disabled). if only one channel is turned off (power-down/standby/output disabled), the fast detect output pins repeat the data of the active channel. coarse upper threshold (register 0x105) bits [7:3]reserved bits [2:0]coarse upper threshold these bits set the level required to assert the coarse upper threshold indication (see tabl e 18 ). fine upper threshold (registe r 0x106 and register 0x107) register 0x106, bits [7:0]fine upper threshold [7:0] register 0x107, bits [7:5]reserved register 0x107, bits [4:0]fine upper threshold [12:8] these registers provide the fine upper limit threshold. this 13-bit value is compared with the 10-bit magnitude from the adc block. if the adc magnitude exceeds this threshold value, the f_ut indicator is set. fine lower threshold (registe r 0x108 and register 0x109) register 0x108, bits [7:0]fine lower threshold [7:0] register 0x109, bits [7:5]reserved register 0x109, bits [4:0]fine lower threshold [12:8] these registers provide a fine lower limit threshold. this 13-bit value is compared with the 10-bit magnitude from the adc block. if the adc magnitude is less than this threshold value, the f_lt indicator is set. AD9600 rev. 0 | page 44 of 72 increase gain dwell time (register 0x10a and register 0x10b) register 0x10a, bits [7:0]increase gain dwell time [7:0] register 0x10b, bits [7:0]increase gain dwell time [15:8] these registers are programmed with the dwell time in adc clock cycles. the signal must be below the fine lower threshold value before the increase gain (ig) indicator is asserted. signal monitor dc correction control (register 0x10c) bit 7reserved bit 6dc correction freeze when bit 6 is set high, the dc correction is not updated to the signal monitor block; therefore, the block continues to hold the last dc value that it calculated. bits [5:2]dc correction bandwidth these bits set the averaging time of the power monitor dc correction function. this 4-bit word sets the bandwidth of the correction block according to the following equation: = ?? 2 2__ 14 clk k f bwcorrdc where: k is the 4-bit value programmed in register 0x10c, bits [5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the AD9600 adc sample rate in hertz. bit 1dc correction for signal path enable setting bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. bit 0dc correction for signal monitor enable bit 0 enables the dc correction function in the signal monitor block. the dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. removing this dc from the measurement allows a more accurate reading. signal monitor dc value channel a (register 0x10d and register 0x10e) register 0x10d, bits [7:0]dc value channel a [7:0] register 0x10e, bits [7:6]reserved register 0x10e, bits [5:0]dc value channel a [13:8] these read-only registers hold the latest dc offset value computed by the signal monitor for channel a. signal monitor dc value channel b (register 0x10f and register 0x110) register 0x10f bits [7:0]dc value channel b [7:0] register 0x110 bits [7:6]reserved register 0x110 bits [5:0]dc value channel b [13:8] these read-only registers hold the latest dc offset value computed by the signal monitor for channel b. signal monitor sport co ntrol (register 0x111) bit 7reserved bit 6rms/ms magnitude output enable these bits enable the 20-bit rms or ms magnitude measurement as output on the sport. bit 5peak detector output enable bit 5 enables the 10-bit peak measurement as output on the sport. bit 4threshold crossing output enable bit 4 enables the 10-bit threshold measurement as output on the sport. bits [3:2]sport smi sclk divide the values of these bits set the sport smi sclk divide ratio from the input clock. a value of 0x01 sets divide by 2 (default), a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8. bit 1 sport smi sclk sleep setting bit 1 high causes the smi sclk to remain low when the signal monitor block has no data to transfer. bit 0signal monitor sport output enable when set, bit 0 enables the sport output of the signal monitor to begin shifting out the result data from the signal monitor block. signal monitor control (register 0x112) bit 7complex power calculation mode enable this mode assumes that i data is present on one channel and q data is present on the opposite channel. the result reported is the complex power, measured as 22 qi + bits [6:4]reserved bit 3signal monitor rms/ms select setting bit 3 low selects rms power measurement mode. setting bit 3 high selects ms power measurement mode. bits [2:1]signal monitor mode bit 2 and bit 1 set the mode of the signal monitor for the data output of register 0x116 to register 0x11b. setting bit 2 and bit 1 to 00 selects rms/ms magnitude output, setting these bits to 01 selects peak power output, and setting to 10 or 11 selects threshold crossing output. bit 0signal monitor enable setting bit 0 high enables the signal monitor block. AD9600 rev. 0 | page 45 of 72 signal monitor period (register 0x113 to register 0x115) register 0x113, bits [7:0]signal monitor period [7:0] register 0x114, bits [7:0]signal monitor period [15:8] register 0x115, bits [7:0]signal monitor period [23:16] this 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. the minimum value for this register is 128 cycles; programmed values less than 128 revert to 128. signal monitor result ch annel a (register 0x116 to register 0x118) register 0x116, bits [7:0 ]signal monitor result channel a [7:0] register 0x117, bits [7:0 ]signal monitor result channel a [15:8] register 0x118, bits [7:4]reserved register 0x118, bits [3:0 ]signal monitor result channel a [19:16] this 20-bit value contains the result calculated by the signal monitoring block for channel a. the content is dependent on the settings in bits [2:1] of register 0x112. signal monitor result channel b (register 0x119 to register 0x11b) register 0x119, bits [7:0] signal monitor result channel b [7:0] register 0x11a, bits [7:0]signal monitor result channel b [15:8] register 0x11b, bits [7:4]reserved register 0x11b, bits [3:0]signal monitor result channel b [19:16] this 20-bit value contains the result calculated by the signal monitoring block for channel b. the content is dependent on the settings in bits [2:1] of register 0x112. AD9600 rev. 0 | page 46 of 72 applications information design guidelines when designing the AD9600 into a system, the designer should, before starting design and layout, become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins. power and ground recommendations when connecting power to the AD9600, the designer should use two separate 1.8 v supplies: one supply should be used for avdd and dvdd and a separate supply for drvdd. the avdd and dvdd supplies, although derived from the same source, should be isolated with a ferrite bead or filter choke and have separate decoupling capacitors. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts pins with minimal trace length. a single pc board ground plane should be sufficient when using the AD9600. with proper decoupling and smart parti- tioning of the pc boards analog, digital, and clock sections, optimum performance can be easily achieved. exposed paddle thermal heat slug recommendations to achieve the best electrical and thermal performance of the AD9600, the exposed paddle on the underside of the adc must be connected to analog ground (agnd). a continuously exposed (no solder mask) copper plane on the pcb should mate to the exposed paddle, pin 0, of the AD9600. in addition, the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb, and these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the adc and pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and pcb. see the evaluation board layout figures ( figure 84 to figure 91 ) for an example of a pcb layout. for detailed information on packaging and the pcb layout of chip scale packages, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . cml the cml pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 47 . rbias the AD9600 requires the user to place a 10 k resistor between the rbias pin and ground. this register sets the master current reference of the adc core and should have at least a 1% tolerance. reference decoupling the vref pin should be externally decoupled to ground with a low-esr 1.0 f capacitor in parallel with a 0.1 f ceramic low- esr capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade the converters performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9600 in order to keep these signals from transitioning at the converter inputs during critical sampling periods. AD9600 rev. 0 | page 47 of 72 evaluation board the AD9600 evaluation board provides all of the support circuitry required to operate the adc in its various modes and configurations. the converter can be driven differentially using the double-balun configuration (default) or an ad8352 differential driver. the adc can also be driven in a single-ended fashion. separate power pins are provided to isolate the dut from the ad8352 drive circuitry. each input configuration can be selected by properly connecting various components (see figure 74 to figure 83 ). figure 73 shows the typical bench characterization setup used to evaluate the ac performance of the AD9600. it is critical that the signal sources used for the analog input and clock have very low phase noise (<<1 ps rms jitter) to realize the optimum performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 74 to figure 91 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. power supplies the evaluation board comes with a wall-mountable switching power supply that provides a 6 v, 2 a maximum output. connect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the output of the supply is a 2.1 mm inner diameter circular jack that connects to the pcb at j16. once on the pc board, the 6 v supply is fused and conditioned before connecting to six low dropout linear regulators that supply the proper bias to each of the various sections of the board. the evaluation board can be operated using external supplies by removing l1, l3, l4, and l13 to disconnect the voltage regulators supplied from the switching power supply. this enables the user to individually bias each section of the board. use p3 and p4 to connect a different supply for each section. at least one 1.8 v supply is needed with a 1 a current capability for avdd and dvdd; a separate 1.8 v to 3.3 v supply is recommended for drvdd. to operate the evaluation board using the ad8352 driver, a separate 5.0 v supply (amp vdd) with a 1 a current capability is needed. to operate the evaluation board using the alternative spi options, a separate 3.3 v analog supply (vs) is needed in addition to the other supplies. the 3.3 v supply (vs) should also have a 1 a current capability. using solder jumper sj35 allows the user to separate avdd and dvdd if desired. input signals when connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as rohde & schwarz sma100a or agilent hp8644 signal generators or the equivalent, as well as a 1 m, shielded, rg-58, 50 coaxial cable. enter the desired frequency and amplitude for the adc. the AD9600 evaluation board from analog devices can accept a ~2.8 v p-p or a 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. good choices of such band-pass filters are available from tte, allen avionics, and k&l microwave, inc. connect the filter directly to the evaluation board, if possible. output signals the parallel cmos outputs interface directly with the analog devices standard adc data capture board (hsc-adc- evalcz). for more information on the adc data capture boards and their optional settings, visit www.analog.com/fifo . usb connection AD9600 evaluation board 10-bit parallel cmos 10-bit parallel cmos hsc-adc-evalcz fpga based data capture board pc running visual analog and spi controller software 1.8v ?+ ?+ avdd in vs drvdd in gnd gnd ?+ 5.0v gnd amp vdd 3.3v 6v dc 2a max wall outlet 100v ac to 240v ac 47hz to 63hz switching power supply ?+ gnd 3.3v vcp ?+ gnd 3.3v spi spi 06909-300 rohde & schwarz, sma100a, 2v p-p signal synthesizer clk rohde & schwarz, sma100a, 2v p-p signal synthesizer ainb band-pass filter rohde & schwarz, sma100a, 2v p-p signal synthesizer aina band-pass filter figure 73. evaluation board connection AD9600 rev. 0 | page 48 of 72 default operation and jumper selection settings the following is a list of the default and optional settings, or modes, allowed on the AD9600 evaluation board. power connect the switching power supply that is provided with the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p500. vin the evaluation board is set up for a double-balun configur- ation analog input with an optimum 50 impedance matching from 70 mhz to 200 mhz. for more bandwidth response, the differential capacitor across the analog inputs can be changed or removed (see tabl e 10 ). the common mode of the analog inputs is developed from the center tap of the transformer via the cml pin of the adc (see the analog input considerations section). vref vref is set to 1.0 v by tying the sense pin to ground and adding a jumper on header j5 (pin 1 to pin 2). this causes the adc to operate in the 2.0 v p-p full-scale range. to place the adc in the 1.0 v p-p mode (vref = 0.5 v), a jumper should be placed on header j4. a separate external reference option is also included on the evaluation board. to use an external reference, connect pin 1 of j6 to pin 2 of j6 and provide an external reference at tp5. proper use of the vref options is detailed in the volt age refe rence section. rbias rbias requires that a 10 k resistor (r503) be connected to ground. this pin is used to set the adc core bias current. clock the default clock input circuitry is derived from a simple balun- coupled circuit using a high bandwidth 1:1 impedance ratio balun (t5) that adds a very low amount of jitter to the clock path. the clock input is 50 terminated and ac-coupled to handle single- ended sine wave inputs. the transformer converts the single-ended input to a differential signal that is clipped before entering the adc clock inputs. when the AD9600 input clock divider is used, clock frequencies up to 625 mhz can be input into the evaluation board through connector s5. pdwn to enable the power-down feature, connect j7, shorting the pdwn pin to avdd. csb the csb pin is internally pulled up, setting the chip into external pin mode, to ignore the sdio and sclk information. to connect the control of the csb pin to the spi circuitry on the evaluation board, connect pin 1 of j21 to pin 2 of j21. sclk/dfs if the spi port is in external pin mode, the sclk/dfs pin sets the data format of the outputs. if the pin is left floating, the pin is internally pulled down, setting the default data format condition to offset binary. connecting pin 1 of j2 to pin 2 of j2 sets the format to twos complement. if the spi port is in serial pin mode, connecting pin 2 of j2 to pin 3 of j2 connects the sclk pin to the on-board spi circuitry (see the serial port interface (spi) section). sdio/dcs if the spi port is in external pin mode, the sdio/dcs pin acts to set the duty cycle stabilizer. if the pin is left floating, the pin is internally pulled up, setting the default condition to dcs enabled. to disable the dcs, connect pin 1 of j1 to pin 2 of j1. if the spi port is in serial pin mode, connecting pin 2 of j1 to pin 3 of j1 connects the sdio pin to the on-board spi circuitry (see the serial port interface (spi) section). alternative clock configurations two clocking options are provided on the AD9600 evaluation board. the first option is to use the on-board crystal oscillator (y1) to provide the clock input to the part. to enable this crystal, resistors r8 (0 ) and r85 (10 k) should be installed and resistors r82 and r30 should be removed. the second option is to use a differential lvpecl clock to drive the adc input using the ad9516-4 (u2). when using this option, the ad9516-4 charge-pump filter components need to be populated (see figure 78 ). consult the ad9516-4 data sheet for more information. to configure the clock input (from s5) to drive the ad9516 reference input instead of directly driving the adc, the following components need to be added, removed, and/or changed. 1. remove r32, r33, r99, and r101 in the default clock path. 2. populate c78 and c79 with 0.001 f capacitors and r78 and r79 with 0 resistors in the clock path. additionally, unused ad9516 outputs (one lvds and one lvpecl) are routed to optional connectors s8 through s11 on the evaluation board. AD9600 rev. 0 | page 49 of 72 alternative analog input drive configuration this section provides a brief description of the alternative analog input drive configuration using the ad8352 . when using this drive option, some additional components need to be populated. for more details on the ad8352 differential driver, including how it works and its optional pin settings, consult the ad8352 data sheet. to configure the analog input to drive the ad8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for channel a. in addition, the corresponding components for channel b should be changed. 1. remove c1, c17, c18, and c117 in the default analog input path. 2. populate c8 and c9 with 0.1 f capacitors in the analog input path. to drive the ad8352 in the differential input mode populate transformer t10; resistors r1, r37, r39, r126, and r127; and capacitors c10, c11, and c125. 3. populate the optional amplifier output path with the desired components, including an optional low-pass filter. install 0 resistors r44 and r48. resistors r43 and r47 should be increased (typically to 100 ) to increase the output impedance seen by the ad8352 to 200 . AD9600 rev. 0 | page 50 of 72 schematics 06909-301 ba ind0603 12 1 2 3 6 5 4 ind0603 12 9 12 enb 15 67 4 3 2 8 13 vcm 14 vin 5 vip 16 von 10 vop 11 ad8352 1 vcc gnd gnd gnd vcc rgn rdn rgp rdp 1 2 5 4 1 2 3 ps f 5 4 1 2 3 ps f 1 1 5 4 1 2 3 ps f ind0603 12 1 2 ind0603 12 dnp dnp dnp optional amplifier input path default amplifier input path ain+ ain- dnp dnp dnp l16 180n h r31 0ohm c16 0.001u r5 57.6ohm r1 57.6ohm r28 57.6ohm r126 4.12 k r27 33ohm r26 33ohm r41 10kohm r40 10kohm s2 amp+a l17 180n h vin-a avdd r50 0ohm vin+a amp+a amp-a ina+ ina- ina- ina+ etc1-1-1 3 t10 c125 .3pf r127 100ohm r121 res0402 0ohm r4 0ohm r48 0ohm r49 0ohm r47 33ohm r43 33ohm r42 0ohm r44 0ohm r110 0ohm r2 0ohm r120 0ohm r39 0ohm r38 dnp r37 0ohm r36 dnp r54 0ohm r35 24.9ohm r29 24.9ohm tp15 tp14 c27 10u c23 0.1u c22 0.1u etc1-1-1 3 t2 etc1-1-1 3 t1 cml cml avdd amp-a ampvdd c9 0.1u c4 18pf c139 12pf c5 4.7pf c12 0.001u c3 0.1u c1 0.1u c8 0.1u c10 0.1u c11 0.1u c47 0.1u c117 0.1u c17 0.1u c18 0.1u c2 0.1u s1 z1 l14 120n h adt1_1w t t7 l15 120n h ampvdd w1 ampvdd figure 74. evaluation board schematic, channel a analog inputs AD9600 rev. 0 | page 51 of 72 06909-302 ba enb vcm vin vip von vop ad8352 vcc gnd gnd gnd vcc rgn rdn rgp rdp ps f ind0603 ind0603 ind0603 ind0603 ps f ps f dnp dnp dnp dnp dnp optional amplifier input path default amplifier input path ain+ ain- dnp r133 dnp r72 57.6ohm r52 57.6ohm r51 57.6ohm r128 4.12 k r73 33ohm r74 33ohm r70 33ohm r71 33ohm r53 10kohm ampvdd r131 10kohm r135 24.9ohm r129 100ohm r69 0ohm r67 0ohm r123 res0402 0ohm r122 res0402 0ohm r111 0ohm r94 0ohm r95 0ohm r96 0ohm r81 0ohm r80 0ohm r55 0ohm r6 0ohm r68 dnp r134 24.9ohm r132 0ohm r66 0ohm 3 2 1 4 5 etc1-1-1 3 t4 4 5 6 3 2 1 adt1_1w t t8 3 2 1 4 5 etc1-1-1 3 t3 c51 0.1u c28 0.1u inb- inb+ cml amp-b amp+b cml vin-b avdd avdd amp-b amp+b ampvdd inb- inb+ c19 18pf c29 12pf c84 4.7pf c128 .3pf c46 0.001u c140 0.001u c38 0.1u c30 0.1u c31 0.1u c82 0.1u c83 0.1u c24 0.1u c7 0.1u c39 0.1u c6 0.1u 2 1 s3 2 1 s4 1 tp16 1 tp17 12 l19 120n h 12 l21 180n h 12 l20 180n h 12 l18 120n h 3 2 1 4 5 etc1-1-1 3 t11 9 12 67 15 4 1 3 2 8 13 5 16 14 10 11 z2 w2 c62 10u c61 0.1u c60 0.1u ampvdd vin+b figure 75. evaluation board schematic, channel b analog inputs AD9600 rev. 0 | page 52 of 72 0 6909-303 ps f enc enc\ vs c145 0.1u c20 0.1u r85 10kohm r8 0ohm 21 tp2 r84 24.9ohm r79 0ohm r34 dnp r101 0ohm r3 0ohm r7 57.6ohm r90 0ohm r30 57.6ohm r32 0ohm r33 0ohm r99 0ohm r78 0ohm r82 10kohm altclk - c64 0.001u c94 0.001u 3 2 1 4 5 etc1-1-1 3 t5 c79 0.001u opt_clk- clk- clk+ opt_clk+ opt_clk+ c77 0.001u c78 0.001u c63 0.001u c56 0.1u c21 0.1u 2 1 sma200u p s6 2 1 sma200u p s5 4 5 6 3 2 1 adt1_1w t t9 opt_clk- altclk + r83 24.9ohm figure 76. evaluation board schematic, dut clock input AD9600 rev. 0 | page 53 of 72 06909-304 tes t test test bypass_ld o clk cp cp_rset gnd_esd gnd_out89_div gnd_ref ld lf nc1 nc2 nc3 nc4 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 refin refmon ref_sel rset_clock sclk sdio sdo status vcp vs_clk_dist vs_out01_div vs_out01_drv vs_out23_div vs_out23_drv vs_out45_div vs_out45_drv vs_out67_1 vs_out67_2 vs_out89_1 vs_out89_2 vs_pll_1 vs_pll_2 vs_prescale r vs_ref vs_vco clkb csb out0b out1b out2b out3b out4b out5b out6b out7b out8b out9b pdb refinb resetb syncb ad9516_64lfcsp pad 2 ad9516 clk in lvds output lvpecl outpu t to adc lvpecl 1 s7 vcxo_clk - r89 49.9ohm r12 4.12 k r9 100ohm r75 100ohm 1 tp8 2 1 s11 out6p out6n 10 13 5 62 44 37 59 3 9 15 18 19 20 56 53 43 40 25 28 48 46 33 35 2 7 58 22 21 6 4 12 51 54 38 41 30 27 49 50 31 32 61 60 57 11 14 17 55 52 42 39 26 29 47 45 34 36 24 63 23 8 1 16 64 u2 200 r91 200 r86 r11 5.1 k 200 r88 200 r92 r125 res0402 0ohm r124 res0402 0ohm r10 0ohm c104 0.1u c101 0.1u c98 0.1u c99 0.1u c96 0.1u c97 0.1u c100 0.1u sync vcp vs_out_d r vcxo_clk + 1 tp18 ld 1 tp19 c80 18pf c141 0.001u c86 0.1u c85 0.1u c87 0.1u c88 0.1u c143 0.1u c142 0.1u 2 1 s10 2 1 s9 2 1 s8 1 tp20 opt_clk + sclk vs syncb resetb opt_clk - pdb csb_2 vs vs vs vs vs vs_out_dr vs_out_d r vs vs_out_d r vcp sdo sdi ref_sel lf agnd agnd agnd cp bypass_ld o status refmon altclk- altclk+ figure 77. evaluation board schematic, optional ad9516 clock circuit AD9600 rev. 0 | page 54 of 72 06909-305 a1 gnd a2 y1 vcc y2 out2 out1 vcc gnd out_disable freq_ctrl_v vs-500 ac val val val val val charge pump filter sync vs vs c144 sel c92 sel c89 sel r93 r87 24.9ohm r98 r136 r137 r97 r117 res0402 0ohm r116 res0402 0ohm r108 res040 2 10kohm r109 res040 2 10kohm r107 res040 2 10kohm r106 res040 2 10kohm r139 res0402 0ohm r114 res0402 0ohm r105 res0402 10kohm r103 res0402 10kohm r102 res0402 10kohm r100 res0402 10kohm sync r104 res0402 0ohm r46 res0402 33ohm 200 r76 r45 res0603 57.6ohm ld reset b sync b pd b ref_se l vs vs vs vs vcxo_clk - vcxo_clk + vcp vcp lf cp 4 5 6 3 2 1 u25 oscvectron_vs50 0 c91 sel c90 sel c25 0.1u c26 0.1u 2 1 sma200u p s12 1 tp1 4 5 6 3 2 1 nl27wz0 4 u3 bypass_ld o figure 78. evaluation board schematic, optional ad9516 loop filter/vco and sync input AD9600 rev. 0 | page 55 of 72 06909-306 28 9 14 60 15 16 61 62 u1 39 43 38 44 37 52 47 48 51 40 42 33 35 34 46 56 32 55 31 54 30 53 29 57 24 21 1 20 64 12 10 11 7 26 6 25 5 23 4 22 3 19 2 18 63 17 59 13 8 27 58 41 50 49 45 36 avdd2 clk+ clk- cml d6a d6b d7a d7b d8a d8b d9a(msb) d9b(msb) d0a d1a d1b d2a d2b d3a d3b d4a d4b d5a d5b dcoa dcob nc drgnd drvdd fd0a fd0b fd1a fd1b fd2a fd2b fd3a fd3b avdd3 smi_sclk/pdw n smi_sdfs smi_sdo/oeb rbias sense spi_csb spi_sclk/dfs spi_sdio/dcs sync vin+a vin+b vin-a vin-b vref d0b(lsb) nc nc nc nc nc (lsb) drgnd drvdd dvdd avdd dvdd nc nc j7 - install for pdwn j8 - installforoutputdisabl e j5 - installforiv vref/2vinputspan j4 - installfor 0.5v vref/iv inputspan j6 - installfor externalreferencemode AD9600 d3a 5 6 7 8 4 3 2 1 22ohm rpak4 r58 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r60 avdd r112 res040 2 0ohm r115 res0402 0ohm r113 res0402 0ohm 1 tp6 r63 res0402 10kohm c15 1u 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r59 fd0b 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r57 fd1b fd2b fd3b spare 1 spare 2 dco b dco a d2a dvdd avdd pwr_sdf s fd0a pwr_sd o pwr_scl k fd3a fd2a fd1a drvdd 1 1 1 1 c109 0.1u c121 0.1u c122 0.001u c126 0.001u c127 0.001u c34 0.1u c33 0.001u c35 0.001u c36 0.1u c32 0.1u c14 0.1u c40 0.1u c120 0.1u 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r61 1 tp3 1 tp5 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r62 dvdd dvdd sync spi_csb clk - clk+ avdd vin+a vin-a vin-b vin+b avdd avdd spi_sdi o spi_scl k drvd d cml drvd d c137 0.001u r64 res0402 0ohm d2a d3a d4a d5a d6a d7a d8a d9a spare 3 spare 4 d0b d1b d2b d3b d4b d5b d6b d7b d8b d9b spare 5 spare 6 spare 7 spare 8 figure 79. evaluation board schematic, dut AD9600 rev. 0 | page 56 of 72 06909-307 test test test test val channela channelb digital/hsc-adc-evalcz interface 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74vcx162244mtd u17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74vcx162244mtd u16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74vcx162244mtd u15 sdi csb sclk r145 res0402 0ohm r142 res040 2 0ohm sdo r141 res040 2 0ohm r119 res040 2 0ohm csb_2 v_dig vs r140 res040 2 10kohm r118 res040 2 10kohm r130 r77 100ohm sync out6n out6p out6p out6n fd0b fd1b dg10 dg9 dg8 dg7 dg6 dg5 dg4 dg3 dg2 dg1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 bg10 bg9 bg8 bg7 bg6 bg5 bg4 bg3 bg2 bg1 tyco_hm-zd j11 v_di g v_di g fd2b fd3b spare 1 spare 2 v_di g v_di g v_dig v_di g v_di g dco b dco a v_di g fd3a fd2a fd1a fd0a v_di g pwr_sdo pwr_sdfs sclk_out sdfs_out sdo_ou t pwr_sclk sdo_ou t 1 tp23 sclk_ou t sdfs_ou t 1 tp21 v_dig c65 0.1u vs c71 0.1u c70 0.1u c69 0.1u c68 0.1u c66 0.1u c67 0.1u c72 0.1u c73 0.1u c76 0.1u c74 0.1u c75 0.1u resetb dg10 dg9 dg8 dg7 dg6 dg5 dg4 dg3 dg2 dg1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 bg10 bg9 bg8 bg7 bg6 bg5 bg4 bg3 bg2 bg1 tyco_hm -zd j12 dg10 dg9 dg8 dg7 dg6 dg5 dg4 dg3 dg2 dg1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 bg10 bg9 bg8 bg7 bg6 bg5 bg4 bg3 bg2 bg1 tyco_hm-zd j10 1 tp22 1 tp24 v_di g r143 res040 2 0ohm r144 res0402 0ohm spare 3 spare 4 d0b d1b d2b d3b d4b d5b d6b d7b d8b d9b spare 5 spare 6 spare 8 spare 7 d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a figure 80. evaluation board sche matic, digital output interface AD9600 rev. 0 | page 57 of 72 06909-308 y1 vcc y2 a1 gnd a2 y1 vcc y2 a1 gnd a2 j1 - jumper pins 2 to 3 for spi operation jumper pins 1 to 2 for dcs enable j2 - jumper pins 2 to 3 for spi operation jumper pins 1 to 2 for twos complement outpu t j21 - install jumper for spi operation 1 3 j2 1 3 j1 csb_2 r23 res0603 100kohm r22 res0603 100kohm r17 res0603 100kohm r65 res0402 10kohm c81 0.1u r24 res0402 10kohm r21 res0603 1kohm r19 res0603 1kohm r18 res0402 10kohm r20 res0603 1kohm c13 0.1u sdi sdo sclk csb v_di g sdi vs sdo v_dig v_dig v_di g spi_sdi o spi_scl k spi_cs b v_di g v_di g v_di g sclk csb 3 2 1 4 5 6 nc7wz16p6 x u8 3 2 1 4 5 6 nc7wz07p6 x u7 figure 81. evaluation board schematic, spi circuitry AD9600 rev. 0 | page 58 of 72 06909-309 1 p1 2 p2 3 p3 4 p4 5 p5 6 p6 p1 p2 p3 p4 smdc110f gnd in pad 4 out ac adp3334 3 fb gnd 5 8 in in2 7 1 out out2 2 sd 6 bias psg cb cg cg cg 6v, 2a max powerinput bnx-016 optionalpowersupplyinputs drvddsetting drvdd r13 r14 3.3 1.8 2.5 140k 107k 76.8k 78.7k 94.0k 147k gnd test points 1 3 2 4 5 6 f1 vr1 21 s2a_rec t cr12 21 s2a_rec t cr11 21 shot_rect cr8 21 s2a_rec t cr7 1 3 adp333 9 vr3 vs drvddi n c103 0.1u sj35 avddi n c102 10u c52 10u vcp f2 pwr_i n 21 s2a_rec t cr10 c42 1u 2 3 1 power_jac k j16 c53 10u c54 10u c41 10u c59 0.1u c58 0.1u c57 0.1u 1 tp4 2 1 10uh ind1210 l3 1 tp25 v_di g dvdd drvd d avdd drvddi n avddi n 1 1 c45 1u c44 1u c43 1u c93 0.001u p4 12 l6 ind1210 10uh 1 tp13 1 tp12 1 tp10 1 tp9 2 1 10uh ind1210 l11 2 1 10uh ind1210 l10 2 1 10uh ind1210 l4 2 1 10uh ind1210 l9 p3 r16 res060 3 261ohm r13 140koh m r14 78.7koh m figure 82. evaluation board schematic, power supply AD9600 rev. 0 | page 59 of 72 06909-310 adp3334 fb gnd in in2 out out2 sd gnd in pad 4 out gnd in pad 4 out gnd in pad 4 out power supply bypass capaci tors 1 3 adp333 9 vr6 1 3 adp333 9 vr5 1 3 adp333 9 vr4 sj36 sj37 c124 10u c118 10u c119 10u c108 0.1u c10 5 0.1u c116 0.1u c107 0.1u c113 0.1u vs c114 0.1u c115 0.1u c111 0.1u c112 0.1u c110 0.1u 2 1 10uh ind1210 l12 ampvdd c129 1u vcp vcp vs vs_out_d r 3 5 8 7 1 2 6 vr2 c135 1u c136 1u c132 1u c131 1u c134 1u c133 1u c130 1u c95 0.001u 2 1 10uh ind1210 l13 2 1 10u h ind1210 l1 2 1 10u h ind1210 l8 pwr_in pwr_in pwr_in pwr_in r15 78.7koh m r25 140koh m vcp vs_out_d r vs figure 83. evaluation board schematic, power supply cont. AD9600 rev. 0 | page 60 of 72 evaluation board layouts 06909-185 figure 84. evaluation board layout, primary side AD9600 rev. 0 | page 61 of 72 0 6909-186 figure 85. evaluation board layout, ground plane AD9600 rev. 0 | page 62 of 72 0 6909-187 figure 86. evaluation board layout, power plane AD9600 rev. 0 | page 63 of 72 0 6909-188 figure 87. evaluation board layout, power plane AD9600 rev. 0 | page 64 of 72 06909-189 figure 88. evaluation board layout, ground plane AD9600 rev. 0 | page 65 of 72 0 6909-190 figure 89. evaluation board layout, secondary side (mirrored image) AD9600 rev. 0 | page 66 of 72 06909-191 figure 90. evaluation board layout, silkscreen, primary side AD9600 rev. 0 | page 67 of 72 0 6909-192 figure 91. evaluation board layo ut, silk screen, secondary side AD9600 rev. 0 | page 68 of 72 bill of materials table 23. evaluation board bill of materials (bom) 1 , 2 item qty reference designator description package manufacturer mfg. part number 1 1 AD9600ce_revb pcb pcb analog devices 2 55 c1 to c3, c6, c7, c13, c14, c17, c18, c20 to c26, c32, c57 to c61, c65 to c76, c81 to c83, c96 to c101, c103, c105, c 107, c108, c110 to c116, c145 0.1 f, 16 v ceramic capacitor, smt 0402 c0402sm murata grm155r71c104ka88d 3 1 c80 18 pf, cog, 50 v, 5% ceramic capacitor, smt 0402 c0402sm murata gjm1555c1h180jb01j 4 2 c5, c84 4.7 pf, cog, 50 v, 5% ceramic capacitor, smt 0402 c0402sm murata gjm1555c1h4r7cb01j 5 10 c33, c35, c63, c93 to c95, c122, c126, c 127, c137 0.001 f, x7r, 25 v, 10% ceramic capacitor, smt 0402 c0402sm murata grm155r71h102ka01d 6 13 c15, c42 to c45, c129 to c136 1 f, x5r, 25 v, 10% ceramic capacitor, smt 0805 c0805 murata gr4m219r61a105kc01d 7 10 c27, c41, c52 to c54, c62, c102, c118, c119, c124 10 f, x5r, 10 v, 10% ceramic capacitor, smt 1206 c1206 murata grm31cr61c106kc31l 8 1 cr5 schottky diode hsms2822, sot23 sot23 avago technologies hsms- 2822-blkg 9 2 cr6, cr9 led red, smt, 0603, ss-type led0603 panasonic lnj208r8ara 10 4 cr7, cr10 to cr12 50 v, 2 a diode do_214aa micro commercial components s2a-tp 11 1 cr8 30 v, 3 a diode do_214ab micro commercial components sk33-tp 12 1 f1 emi filter flthmuratabnx01 murata bnx016-01 13 1 f2 6.0 v, 3.0 a, trip current resettable fuse l1206 tyco raychem nanosmdc150f-2 14 2 j1 to j2 3-pin, male, single row, straight header hdr3 samtec tws-1003-08-g-s 15 9 j4 to j9, j18, j19, j21 2-pin, male, straight header hdr2 samtec tws-102-08-g-s 16 3 j10 to j12 interface connect or tyco_hm_zd tyco 6469169-1 17 1 j14 8-pin, male, double row, straight header cnberg2x4h350ld samtec tsw-104-08-t-d 18 1 j16 dc power jack connector pwr_jack1 cui stack pj-002a 19 10 l1, l3, l4, l6, l8 to l13 10 h, 2 a bead core, 1210 1210 panasonic exc-cl3225u1 20 1 p3 6-terminal connector ptmicro6 weiland electric, inc. z5.531.3625.0 21 1 p4 4-terminal connector ptmicro4 weiland electric, inc. z5.531.3425.0 22 3 r7, r30, r45 57.6 , 0603, 1/10 w, 1% resistor r0603 nic components nrc06f57r6trf 23 27 r2, r3, r4, r32, r33, r42, r64, r67, r69, r90, r96, r99, r101, r104, r110 to r113, r115, r119, r121, r123, r141 to r145 0 , 1/16 w, 5% resistor r0402sm nic components nrc04zotrf 24 2 r13, r25 140 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f1403trf 25 2 r14, r15 78.7 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f 7872trf AD9600 rev. 0 | page 69 of 72 item qty reference designator description package manufacturer mfg. part number 26 1 r16 261 , 0603, 1/10 w, 1% resistor r0603 nic components nrc06f 2610trf 27 3 r17, r22, r23 100 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f 1003trf 28 7 r18, r24, r63, r65, r82, r118, r140 10 k, 0402, 1/16 w, 1% resistor r0402sm nic components nrc04f 1002trf 29 3 r19, r20, r21 1 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f 1001trf 30 9 r26, r27, r43, r46, r47, r70, r71, r73, r74 33 , 0402, 1/16 w, 5% resistor r0402sm nic components nrc04j330trf 31 5 r57, r59 to r62 22 , 16-pin, 8-resistor, resistor array r_742 cts corporation 742c163220jptr 32 1 r58 22 , 8-pin, 4-resistor, resistor array res_arry cts corporation 742c083220jptr 33 1 r76 200 , 0402, 1/16 w, 1% resistor r0402sm nic components ncr04f 2000trf 34 4 s2, s3, s5 ,s12 sma, inline, male, coaxial connector sma_edge emerson network power 142-0701-201 35 1 sj35 0 , 1/8 w, 1% resistor sldr_pad2muylar nic components nrc10zotrf 36 5 t1 to t5 balun tran6b m/a-com maba-007159-000000 37 1 u1 ic, AD9600 lfcsp64-9x9-9e analog devices AD9600bcpz 38 1 u2 clock distribution, pll ic lfc sp64-9x9 analog devices ad9516-4bcpz 39 1 u3 dual inverter ic sc70_6 fairchild semiconductor nc7wz04p6x_nl 40 1 u7 dual buffer ic, open-drain circuits sc70_6 fairchild semiconductor nc7wz07p6x_nl 41 1 u8 uhs dual buffer ic sc70_6 fairchild semiconductor nc7wz16p6x_nl 42 3 u15 to u17 16-bit cmos buffer ic tsop48_8_ 1mm fairchild semiconductor 74vcx16244mtdx_nl 43 2 vr1, vr2 adjustable regulator lfc sp8-3x3 analog devices adp3334acpz 44 1 vr3 1.8 v high accuracy regulator so t223-hs analog devices adp3339akcz-1.8 45 1 vr4 5.0 v high accuracy regulator so t223-hs analog devices adp3339akcz-5.0 46 2 vr5, vr6 3.3 v high accuracy regulato r sot223-hs analog de vices adp3339akcz-3.3 47 1 y1 oscillator clock, vfac3 osc- cts-cb3 valpey fisher vfac3-bhl 48 2 z1, z2 high speed ic, op amp lfcsp16-3x3-pad analog devices ad8352acpz 1 this bill of materials is rohs compliant. 2 the bill of materials lists only those items that are normally installed in the default condition. items that are not installe d are not included in the bom. AD9600 rev. 0 | page 70 of 72 outline dimensions compliant to jedec standards mo-220-vmmd-4 051007-c 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator 7.25 7.10 sq 6.95 pin 1 indicator 0.30 0.23 0.18 figure 92. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-3) dimensions shown in millimeters ordering guide model temperature range package description package option AD9600bcpz-150 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 AD9600bcpz-125 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 AD9600bcpz-105 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 AD9600-150ebz 1 evaluation board with AD9600 and software 1 z = rohs compliant part. AD9600 rev. 0 | page 71 of 72 notes AD9600 rev. 0 | page 72 of 72 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06909-0-11/07(0) |
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